All of lore.kernel.org
 help / color / mirror / Atom feed
From: Herve Codina <herve.codina@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected
Date: Wed, 17 Nov 2021 14:47:15 +0100	[thread overview]
Message-ID: <20211117144715.731a9856@bootlin.com> (raw)
In-Reply-To: <20211112163859.23a2487a@xps13>

Hi,

On Fri, 12 Nov 2021 16:38:59 +0100
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hi Hervé,
> 
> herve.codina@bootlin.com wrote on Fri, 12 Nov 2021 15:38:53 +0100:
> 
> > Some data transfers are expected on 8 bits by the nand core.
> > The fsmc driver did not check this constraint and these transfers
> > can be done on 32 bits depending on buffer alignment and transfers
> > data size.
> > 
> > This patch ensures that these transfers will be 8bits transfers in
> > all cases.  
> 
> I believe there is a misunderstanding here: NAND buses -between the
> NAND controller and the NAND chip- are either 8-bit or 16-bit wide and
> the amount of bytes that you will retrieve per register read is not
> related to it.
> 
> When the controller supports 16-bit accesses, there are certain
> operations that must be performed using only the lowest 8 bits of the
> NAND bus, such as reading a status [1]. In this case, the controller
> must have a way to disable the 16-bit mode temporarily. See [2] and [3]
> for an example. Reading with readb() or readl() will IMHO not impact the
> amount of data lines used for the operation.
> 

Indeed, I misunderstood the force_8bit usage.
This patch is not needed and will be simply removed in v2 series.

Thanks,
Hervé

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Herve Codina <herve.codina@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected
Date: Wed, 17 Nov 2021 14:47:15 +0100	[thread overview]
Message-ID: <20211117144715.731a9856@bootlin.com> (raw)
In-Reply-To: <20211112163859.23a2487a@xps13>

Hi,

On Fri, 12 Nov 2021 16:38:59 +0100
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hi Hervé,
> 
> herve.codina@bootlin.com wrote on Fri, 12 Nov 2021 15:38:53 +0100:
> 
> > Some data transfers are expected on 8 bits by the nand core.
> > The fsmc driver did not check this constraint and these transfers
> > can be done on 32 bits depending on buffer alignment and transfers
> > data size.
> > 
> > This patch ensures that these transfers will be 8bits transfers in
> > all cases.  
> 
> I believe there is a misunderstanding here: NAND buses -between the
> NAND controller and the NAND chip- are either 8-bit or 16-bit wide and
> the amount of bytes that you will retrieve per register read is not
> related to it.
> 
> When the controller supports 16-bit accesses, there are certain
> operations that must be performed using only the lowest 8 bits of the
> NAND bus, such as reading a status [1]. In this case, the controller
> must have a way to disable the 16-bit mode temporarily. See [2] and [3]
> for an example. Reading with readb() or readl() will IMHO not impact the
> amount of data lines used for the operation.
> 

Indeed, I misunderstood the force_8bit usage.
This patch is not needed and will be simply removed in v2 series.

Thanks,
Hervé

  reply	other threads:[~2021-11-17 13:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-12 14:38 [PATCH 0/4] mtd: rawnand: Fixes nand infra delay setting and FSMC nand controller Herve Codina
2021-11-12 14:38 ` Herve Codina
2021-11-12 14:38 ` [PATCH 1/4] mtd: rawnand: Fix nand_erase_op delay Herve Codina
2021-11-12 14:38   ` Herve Codina
2021-11-12 14:38 ` [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected Herve Codina
2021-11-12 14:38   ` Herve Codina
2021-11-12 15:38   ` Miquel Raynal
2021-11-12 15:38     ` Miquel Raynal
2021-11-17 13:47     ` Herve Codina [this message]
2021-11-17 13:47       ` Herve Codina
2021-11-12 14:38 ` [PATCH 3/4] mtd: rawnand: fsmc: Take instruction delay into account Herve Codina
2021-11-12 14:38   ` Herve Codina
2021-11-12 14:38 ` [PATCH 4/4] mtd: rawnand: fsmc: Fix timing computation Herve Codina
2021-11-12 14:38   ` Herve Codina
2021-11-12 15:52   ` Miquel Raynal
2021-11-12 15:52     ` Miquel Raynal

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211117144715.731a9856@bootlin.com \
    --to=herve.codina@bootlin.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=miquel.raynal@bootlin.com \
    --cc=richard@nod.at \
    --cc=thomas.petazzoni@bootlin.com \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.