Re: [PATCH v4 3/6] clk: qcom: Add SDX65 GCC support

[Vamsi Krishna Lanka <quic_vamslank@quicinc.com>]

On Tue, Nov 16, 2021 at 02:03:02PM +0530, Vinod Koul wrote:
> On 15-11-21, 23:38, quic_vamslank@quicinc.com wrote:
> > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
> > 
> > Add Global Clock Controller (GCC) support for SDX65 SoCs from Qualcomm.
> > 
> > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
> > Reported-by: kernel test robot <lkp@intel.com>
> 
> Missing support reported ??

Not mising support but it reported to delete unused varaibles and after
the fix mentioned to add the reported tag.

> 
> > +static struct clk_branch gcc_ahb_pcie_link_clk = {
> > +	.halt_reg = 0x2e004,
> > +	.halt_check = BRANCH_HALT,
> > +	.clkr = {
> > +		.enable_reg = 0x2e004,
> > +		.enable_mask = BIT(0),
> > +		.hw.init = &(struct clk_init_data){
> > +			.name = "gcc_ahb_pcie_link_clk",
> > +			.flags = CLK_IS_CRITICAL,
> > +			.ops = &clk_branch2_ops,
> > +		},
> 
> If this clk is critical then why model in linux, enable directly in probe
> and leave it...?

Yes, actually i have the code which is enabling it directly inside the probe function.
so i will remove it here.

> 
> > +static struct clk_branch gcc_pcie_0_clkref_en = {
> > +	.halt_reg = 0x88004,
> > +	.halt_check = BRANCH_HALT_DELAY,
> 
> Why delay, add a comment at least for that

sure, will do

> > +	.clkr = {
> > +		.enable_reg = 0x88004,
> > +		.enable_mask = BIT(0),
> > +		.hw.init = &(struct clk_init_data){
> > +			.name = "gcc_pcie_0_clkref_en",
> > +			.ops = &clk_branch2_ops,
> > +		},
> > +	},
> > +};
> > +
> > +static struct clk_branch gcc_pcie_aux_clk = {
> > +	.halt_reg = 0x43034,
> > +	.halt_check = BRANCH_HALT_DELAY,
> 
> Here too

will do.

> 
> > +static struct clk_branch gcc_pcie_mstr_axi_clk = {
> > +	.halt_reg = 0x43024,
> > +	.halt_check = BRANCH_HALT_VOTED,
> > +	.hwcg_reg = 0x43024,
> > +	.hwcg_bit = 1,
> > +	.clkr = {
> > +		.enable_reg = 0x6d010,
> > +		.enable_mask = BIT(1),
> > +		.hw.init = &(struct clk_init_data){
> > +			.name = "gcc_pcie_mstr_axi_clk",
> > +			.ops = &clk_branch2_ops,
> > +		},
> > +	},
> > +};
> > +
> > +static struct clk_branch gcc_pcie_pipe_clk = {
> > +	.halt_reg = 0x4303c,
> > +	.halt_check = BRANCH_HALT_DELAY,
> 
> here as well and few more places I guess
> 
> > +static struct clk_branch gcc_xo_pcie_link_clk = {
> > +	.halt_reg = 0x2e008,
> > +	.halt_check = BRANCH_HALT,
> > +	.hwcg_reg = 0x2e008,
> > +	.hwcg_bit = 1,
> > +	.clkr = {
> > +		.enable_reg = 0x2e008,
> > +		.enable_mask = BIT(0),
> > +		.hw.init = &(struct clk_init_data){
> > +			.name = "gcc_xo_pcie_link_clk",
> > +			.flags = CLK_IS_CRITICAL,
> 
> Here as well

Same as above.


> -- 
> ~Vinod