* [PATCH 02/16] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 03/16] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3 Konrad Dybcio
` (14 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add the missing third QUPv3 master node.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index ee183f00dbaf..6cfe1f38dae9 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -597,6 +597,18 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ qupv3_id_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 03/16] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
2021-11-14 1:27 ` [PATCH 02/16] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2 Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Konrad Dybcio
` (13 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
The redistributor properties were missing. Add them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 6cfe1f38dae9..a30ba3193d84 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1020,6 +1020,8 @@ intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x20000>;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
2021-11-14 1:27 ` [PATCH 02/16] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2 Konrad Dybcio
2021-11-14 1:27 ` [PATCH 03/16] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3 Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-30 2:05 ` Stephen Boyd
2021-11-14 1:27 ` [PATCH 05/16] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Konrad Dybcio
` (12 subsequent siblings)
15 siblings, 1 reply; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a30ba3193d84..60866a20a55c 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2484,5 +2484,6 @@ timer {
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
};
};
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-11-14 1:27 ` [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Konrad Dybcio
@ 2021-11-30 2:05 ` Stephen Boyd
2021-11-30 19:59 ` Konrad Dybcio
0 siblings, 1 reply; 24+ messages in thread
From: Stephen Boyd @ 2021-11-30 2:05 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Quoting Konrad Dybcio (2021-11-13 17:27:43)
> Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index a30ba3193d84..60866a20a55c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -2484,5 +2484,6 @@ timer {
> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
Does the firmware not set the frequency properly?
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-11-30 2:05 ` Stephen Boyd
@ 2021-11-30 19:59 ` Konrad Dybcio
2021-12-01 20:45 ` Stephen Boyd
0 siblings, 1 reply; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-30 19:59 UTC (permalink / raw)
To: Stephen Boyd, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
linux-arm-msm, devicetree, linux-kernel
On 30/11/2021 03:05, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-11-13 17:27:43)
>> Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> index a30ba3193d84..60866a20a55c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> @@ -2484,5 +2484,6 @@ timer {
>> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
> Does the firmware not set the frequency properly?
It does on my device on the current firmware version (it wouldn't really
boot if it didn't, no?),
but who knows if it always will, or if it always has been..
It's present in downstream too, so I reckon it does not hurt to have it
here too, even
for completeness-of-describing-the-machine-properly sake.
Konrad
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-11-30 19:59 ` Konrad Dybcio
@ 2021-12-01 20:45 ` Stephen Boyd
2021-12-02 0:00 ` Konrad Dybcio
0 siblings, 1 reply; 24+ messages in thread
From: Stephen Boyd @ 2021-12-01 20:45 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
linux-arm-msm, devicetree, linux-kernel
Quoting Konrad Dybcio (2021-11-30 11:59:03)
>
> On 30/11/2021 03:05, Stephen Boyd wrote:
> > Quoting Konrad Dybcio (2021-11-13 17:27:43)
> >> Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> >> ---
> >> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >> index a30ba3193d84..60866a20a55c 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >> @@ -2484,5 +2484,6 @@ timer {
> >> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> >> + clock-frequency = <19200000>;
> > Does the firmware not set the frequency properly?
>
> It does on my device on the current firmware version (it wouldn't really
> boot if it didn't, no?),
>
> but who knows if it always will, or if it always has been..
>
>
> It's present in downstream too, so I reckon it does not hurt to have it
> here too, even
>
> for completeness-of-describing-the-machine-properly sake.
>
No. We don't want dts files to have this. The property is only there to
workaround bad firmware that doesn't set the frequency. Please drop this
patch.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-12-01 20:45 ` Stephen Boyd
@ 2021-12-02 0:00 ` Konrad Dybcio
2021-12-02 0:17 ` Bjorn Andersson
0 siblings, 1 reply; 24+ messages in thread
From: Konrad Dybcio @ 2021-12-02 0:00 UTC (permalink / raw)
To: Stephen Boyd, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
linux-arm-msm, devicetree, linux-kernel
On 01.12.2021 21:45, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-11-30 11:59:03)
>> On 30/11/2021 03:05, Stephen Boyd wrote:
>>> Quoting Konrad Dybcio (2021-11-13 17:27:43)
>>>> Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>>>> index a30ba3193d84..60866a20a55c 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>>>> @@ -2484,5 +2484,6 @@ timer {
>>>> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>>> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>>>> + clock-frequency = <19200000>;
>>> Does the firmware not set the frequency properly?
>> It does on my device on the current firmware version (it wouldn't really
>> boot if it didn't, no?),
>>
>> but who knows if it always will, or if it always has been..
>>
>>
>> It's present in downstream too, so I reckon it does not hurt to have it
>> here too, even
>>
>> for completeness-of-describing-the-machine-properly sake.
>>
> No. We don't want dts files to have this. The property is only there to
> workaround bad firmware that doesn't set the frequency. Please drop this
> patch.
After looking at it again, I see I was indeed wrong, and so was this patch.
Sorry, and green light for dropping..
Konrad
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
2021-12-02 0:00 ` Konrad Dybcio
@ 2021-12-02 0:17 ` Bjorn Andersson
0 siblings, 0 replies; 24+ messages in thread
From: Bjorn Andersson @ 2021-12-02 0:17 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Stephen Boyd, ~postmarketos/upstreaming, martin.botka,
angelogioacchino.delregno, marijn.suijten, jamipkettunen,
Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel
On Wed 01 Dec 16:00 PST 2021, Konrad Dybcio wrote:
>
> On 01.12.2021 21:45, Stephen Boyd wrote:
> > Quoting Konrad Dybcio (2021-11-30 11:59:03)
> >> On 30/11/2021 03:05, Stephen Boyd wrote:
> >>> Quoting Konrad Dybcio (2021-11-13 17:27:43)
> >>>> Arch timer runs at 19.2 MHz. Specify the rate in the timer node.
> >>>>
> >>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> >>>> ---
> >>>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
> >>>> 1 file changed, 1 insertion(+)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >>>> index a30ba3193d84..60866a20a55c 100644
> >>>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >>>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> >>>> @@ -2484,5 +2484,6 @@ timer {
> >>>> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >>>> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >>>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> >>>> + clock-frequency = <19200000>;
> >>> Does the firmware not set the frequency properly?
> >> It does on my device on the current firmware version (it wouldn't really
> >> boot if it didn't, no?),
> >>
> >> but who knows if it always will, or if it always has been..
> >>
> >>
> >> It's present in downstream too, so I reckon it does not hurt to have it
> >> here too, even
> >>
> >> for completeness-of-describing-the-machine-properly sake.
> >>
> > No. We don't want dts files to have this. The property is only there to
> > workaround bad firmware that doesn't set the frequency. Please drop this
> > patch.
>
> After looking at it again, I see I was indeed wrong, and so was this patch.
>
> Sorry, and green light for dropping..
>
Can you please send me a patch that reverts the change as I merged it
into my -next branch already? Both to simplify for me and to document
why it shouldn't be here for others to refer to in the future.
Thanks,
Bjorn
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/16] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (2 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 06/16] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name Konrad Dybcio
` (11 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as
the &pdc-nth range of the main interrupt controller (GIC). Fix it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 43c8ecb85d17..8fcf04edbf30 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -842,7 +842,7 @@ tsens0: thermal-sensor@c263000 {
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
#qcom,sensors = <16>;
- interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
@@ -853,7 +853,7 @@ tsens1: thermal-sensor@c265000 {
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
#qcom,sensors = <16>;
- interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 60866a20a55c..f3e8549c6572 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -923,7 +923,7 @@ tsens0: thermal-sensor@c263000 {
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
#qcom,sensors = <15>;
- interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
@@ -934,7 +934,7 @@ tsens1: thermal-sensor@c265000 {
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
#qcom,sensors = <14>;
- interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 06/16] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (3 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 05/16] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 07/16] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage Konrad Dybcio
` (10 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Thermal zone names should not be longer than 20 names, which is indicated by
a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to
fix it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index f3e8549c6572..7e0aa4c25094 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2462,7 +2462,7 @@ camera1_alert0: trip-point0 {
};
};
- camera-thermal-bottom {
+ cam-thermal-bottom {
polling-delay-passive = <250>;
polling-delay = <1000>;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 07/16] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (4 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 06/16] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 08/16] arm64: dts: qcom: sm8350: Describe GCC dependency clocks Konrad Dybcio
` (9 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Disable PON/RESIN keys by default and keep the RESIN keycode set-per-board, as
these settings are not common between devices (one cannot even assume all
devices have buttons nowadays..).
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/pmk8350.dtsi | 7 ++++---
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 9 +++++++++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
index 769f9726806f..0f94c46a1444 100644
--- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
@@ -19,16 +19,17 @@ pmk8350_pon: pon@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>;
- pwrkey {
+ pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
+ status = "disabled";
};
- resin {
+ pon_resin: resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
- linux,code = <KEY_VOLUMEDOWN>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
index 122c282a62df..52cf3045602f 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
@@ -289,6 +289,15 @@ &pmk8350_rtc {
status = "okay";
};
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 08/16] arm64: dts: qcom: sm8350: Describe GCC dependency clocks
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (5 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 07/16] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 09/16] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs Konrad Dybcio
` (8 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add all the clock names that the GCC driver expects to get via DT, so that the
clock handles can be filled as the development progresses.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 7e0aa4c25094..3d0d80e61405 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -584,8 +584,30 @@ gcc: clock-controller@100000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- clock-names = "bi_tcxo", "sleep_clk";
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "sleep_clk",
+ "pcie_0_pipe_clk",
+ "pcie_1_pipe_clk",
+ "ufs_card_rx_symbol_0_clk",
+ "ufs_card_rx_symbol_1_clk",
+ "ufs_card_tx_symbol_0_clk",
+ "ufs_phy_rx_symbol_0_clk",
+ "ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk",
+ "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
};
ipcc: mailbox@408000 {
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 09/16] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (6 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 08/16] arm64: dts: qcom: sm8350: Describe GCC dependency clocks Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 10/16] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs Konrad Dybcio
` (7 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 287 +++++++++++++++++++++++++++
1 file changed, 287 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 3d0d80e61405..4b864fcb04e0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -619,6 +619,25 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ qup_opp_table_100mhz: qup-100mhz-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -642,6 +661,84 @@ qupv3_id_0: geniqup@9c0000 {
ranges;
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart2: serial@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x0098c000 0 0x4000>;
@@ -650,6 +747,140 @@ uart2: serial@98c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default_state>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* QUP no. 3 seems to be strictly SPI-only */
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_default>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_default>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_default>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1017,6 +1248,62 @@ tx {
};
};
+ qup_uart6_default: qup-uart6-default {
+ pins = "gpio30", "gpio31";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c0_default: qup-i2c0-default {
+ pins = "gpio4", "gpio5";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_default: qup-i2c1-default {
+ pins = "gpio8", "gpio9";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_default: qup-i2c2-default {
+ pins = "gpio12", "gpio13";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_default: qup-i2c4-default {
+ pins = "gpio20", "gpio21";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_default: qup-i2c5-default {
+ pins = "gpio24", "gpio25";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_default: qup-i2c6-default {
+ pins = "gpio28", "gpio29";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_default: qup-i2c7-default {
+ pins = "gpio32", "gpio33";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_i2c13_default_state: qup-i2c13-default-state {
mux {
pins = "gpio0", "gpio1";
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 10/16] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (7 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 09/16] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 11/16] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs Konrad Dybcio
` (6 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 213 +++++++++++++++++++++++++--
1 file changed, 202 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 4b864fcb04e0..033d3984d572 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -638,6 +638,25 @@ opp-100000000 {
};
};
+ qup_opp_table_120mhz: qup-120mhz-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -898,18 +917,161 @@ qupv3_id_1: geniqup@ac0000 {
ranges;
status = "disabled";
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_default>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_default>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_default>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_default>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_i2c13_default_state>;
+ pinctrl-0 = <&qup_i2c13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
apps_smmu: iommu@15000000 {
@@ -1304,17 +1466,46 @@ qup_i2c7_default: qup-i2c7-default {
bias-disable;
};
- qup_i2c13_default_state: qup-i2c13-default-state {
- mux {
- pins = "gpio0", "gpio1";
- function = "qup13";
- };
+ qup_i2c8_default: qup-i2c8-default {
+ pins = "gpio36", "gpio37";
+ function = "qup8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- config {
- pins = "gpio0", "gpio1";
- drive-strength = <2>;
- bias-pull-up;
- };
+ qup_i2c9_default: qup-i2c9-default {
+ pins = "gpio40", "gpio41";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_default: qup-i2c10-default {
+ pins = "gpio44", "gpio45";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c11_default: qup-i2c11-default {
+ pins = "gpio48", "gpio49";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c12_default: qup-i2c12-default {
+ pins = "gpio52", "gpio53";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c13_default: qup-i2c13-default {
+ pins = "gpio0", "gpio1";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-pull-up;
};
};
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 11/16] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (8 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 10/16] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 12/16] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs Konrad Dybcio
` (5 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 200 +++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 033d3984d572..944ad864f73e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -667,6 +667,164 @@ qupv3_id_2: geniqup@8c0000 {
#size-cells = <2>;
ranges;
status = "disabled";
+
+ i2c14: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_default>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi14: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00880000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_default>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi15: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00884000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c16_default>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi16: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00888000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c17_default>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi17: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* QUP no. 18 seems to be strictly SPI/UART-only */
+
+ spi18: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart18: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart18_default>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c19_default>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi19: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
qupv3_id_0: geniqup@9c0000 {
@@ -1417,6 +1575,13 @@ qup_uart6_default: qup-uart6-default {
bias-disable;
};
+ qup_uart18_default: qup-uart18-default {
+ pins = "gpio58", "gpio59";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_i2c0_default: qup-i2c0-default {
pins = "gpio4", "gpio5";
function = "qup0";
@@ -1507,6 +1672,41 @@ qup_i2c13_default: qup-i2c13-default {
drive-strength = <2>;
bias-pull-up;
};
+
+ qup_i2c14_default: qup-i2c14-default {
+ pins = "gpio56", "gpio57";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c15_default: qup-i2c15-default {
+ pins = "gpio60", "gpio61";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c16_default: qup-i2c16-default {
+ pins = "gpio64", "gpio65";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c17_default: qup-i2c17-default {
+ pins = "gpio72", "gpio73";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c19_default: qup-i2c19-default {
+ pins = "gpio76", "gpio77";
+ function = "qup19";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
rng: rng@10d3000 {
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 12/16] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (9 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 11/16] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Konrad Dybcio
` (4 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Assign the iommus property to allow access to QUP hosts that were not set up by
the bootloader.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 944ad864f73e..0ea735d0df49 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -663,6 +663,7 @@ qupv3_id_2: geniqup@8c0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x5e3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -833,6 +834,7 @@ qupv3_id_0: geniqup@9c0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x5a3 0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -1070,6 +1072,7 @@ qupv3_id_1: geniqup@ac0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x43 0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (10 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 12/16] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 19:47 ` Trilok Soni
2021-11-14 1:27 ` [PATCH 14/16] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes Konrad Dybcio
` (3 subsequent siblings)
15 siblings, 1 reply; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck,
linux-arm-msm, devicetree, linux-kernel
Add support for SONY Xperia 1 III (PDX215) and 5 III (PDX214) smartphones.
Both are based on the SM8350 Sagami platform and feature some really high-end
specs, such as:
- 4K (1 III / PRO-I) / 1080p (5 III), 120Hz HDR OLED 10-bit panels
- USB-C 3.1 with HDMI in (yes, phone as display!) and DP out
- 5G
- 8 or 12 gigs of ram, 128/256/512 gigs of storage
- A 3.5mm headphone jack, a RGB notification LED and a uSD card slot :)
- IP65/68 dust/water resistance
- Dual front-firing speakers and a lot of microphones
- Crazy complex camera hardware (especially on the PRO-I), which includes
4 cameras, an RGBIR sensor and a 3D iToF
The aforementioned PRO-I (PDX217) is not supported in this patch, because
even though it shares most of the code with 1 III, nobody really has it (yet?)
This only adds basic support for booting to a USB shell with a
bootloader-enabled display, support for all the awesome hardware listed above
will (hopefully) come (hopefully) soon.
In order to get a working boot image, you need to run (e.g. for 1 III):
cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8350-sony-xperia-\
sagami-pdx215.dtb > .Image.gz-dtb
mkbootimg \
--kernel .Image.gz-dtb \
--ramdisk some_initrd.img \
--pagesize 4096 \
--base 0x0 \
--kernel_offset 0x8000 \
--ramdisk_offset 0x1000000 \
--tags_offset 0x100 \
--cmdline "SOME_CMDLINE" \
--dtb_offset 0x1f00000 \
--header_version 1 \
--os_version 11 \
--os_patch_level 2021-10 \ # or newer
-o boot.img-sony-xperia-pdx215
Then, you need to flash it on the device and get rid of all the
vendor_boot/dtbo mess:
fastboot flash boot boot.img-sony-xperia-pdx215
fastboot erase vendor_boot
fastboot flash dtbo emptydtbo.img
fastboot reboot
Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing
a "fastboot erase" won't cut it, the bootloader will go crazy and things will
fall apart when it tries to overlay random bytes from an empty partition onto a
perfectly good appended DTB.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../qcom/sm8350-sony-xperia-sagami-pdx214.dts | 19 +++
.../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 13 ++
.../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 132 ++++++++++++++++++
4 files changed, 166 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index bc38b79f4b5b..3a825bdc9052 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -110,3 +110,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts
new file mode 100644
index 000000000000..cc650508dc2d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8350-sony-xperia-sagami.dtsi"
+
+/ {
+ model = "Sony Xperia 5 III";
+ compatible = "sony,pdx214-generic", "qcom,sm8350";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
new file mode 100644
index 000000000000..d21bbeb603a6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8350-sony-xperia-sagami.dtsi"
+
+/ {
+ model = "Sony Xperia 1 III";
+ compatible = "sony,pdx215-generic", "qcom,sm8350";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
new file mode 100644
index 000000000000..b50f04ffee95
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include "sm8350.dtsi"
+#include "pm8350.dtsi"
+#include "pm8350b.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
+#include "pmr735a.dtsi"
+#include "pmr735b.dtsi"
+
+/ {
+ /*
+ * Yes, you are correct, there is NO MORE {msm,board,pmic}-id on SM8350!
+ * Adding it will cause the bootloader to go crazy and randomly crash
+ * shortly after closing UEFI boot services.. Perhaps that has something
+ * to do with the OS running inside a VM now..?
+ */
+
+ chassis-type = "handset";
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@e1000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0xe1000000 0 0x2300000>;
+
+ /* The display, even though it's 4K, initializes at 1080-ish p */
+ width = <1096>;
+ height = <2560>;
+ stride = <(1096 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's (going to be) a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet
+ */
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */
+
+ vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: memory@e1000000 {
+ reg = <0 0xe1000000 0 0x2300000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0 0xffc00000 0 0x100000>;
+ console-size = <0x40000>;
+ record-size = <0x1000>;
+ no-map;
+ };
+ };
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEUP>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <44 4>;
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */
+&usb_1 {
+ status = "okay";
+
+ qcom,select-utmi-as-pipe-clk;
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+
+ maximum-speed = "high-speed";
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III
2021-11-14 1:27 ` [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Konrad Dybcio
@ 2021-11-14 19:47 ` Trilok Soni
2021-11-15 10:26 ` Konrad Dybcio
0 siblings, 1 reply; 24+ messages in thread
From: Trilok Soni @ 2021-11-14 19:47 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck, linux-arm-msm,
devicetree, linux-kernel
Hi Konrad,
On 11/13/2021 5:27 PM, Konrad Dybcio wrote:
>
> Then, you need to flash it on the device and get rid of all the
> vendor_boot/dtbo mess:
>
> fastboot flash boot boot.img-sony-xperia-pdx215
> fastboot erase vendor_boot
> fastboot flash dtbo emptydtbo.img
> fastboot reboot
>
> Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing
> a "fastboot erase" won't cut it, the bootloader will go crazy and things will
> fall apart when it tries to overlay random bytes from an empty partition onto a
> perfectly good appended DTB.
I will check on this part and see if we can make simpler support
fastboot erase dtbo without the extra emptydtbo.
---Trilok Soni
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III
2021-11-14 19:47 ` Trilok Soni
@ 2021-11-15 10:26 ` Konrad Dybcio
0 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-15 10:26 UTC (permalink / raw)
To: Trilok Soni, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck, linux-arm-msm,
devicetree, linux-kernel
On 14/11/2021 20:47, Trilok Soni wrote:
> Hi Konrad,
>
> On 11/13/2021 5:27 PM, Konrad Dybcio wrote:
>>
>> Then, you need to flash it on the device and get rid of all the
>> vendor_boot/dtbo mess:
>>
>> fastboot flash boot boot.img-sony-xperia-pdx215
>> fastboot erase vendor_boot
>> fastboot flash dtbo emptydtbo.img
>> fastboot reboot
>>
>> Where emptydtbo.img is a tiny file that consists of 2 bytes (all
>> zeroes), doing
>> a "fastboot erase" won't cut it, the bootloader will go crazy and
>> things will
>> fall apart when it tries to overlay random bytes from an empty
>> partition onto a
>> perfectly good appended DTB.
>
>
> I will check on this part and see if we can make simpler support
> fastboot erase dtbo without the extra emptydtbo.
>
> ---Trilok Soni
Hi Trilok,
that sounds great, thanks for looking into it! Could you also check why
using a boot.img header version 2 (with a dtb embedded into the boot
image using the --dtb option in mkbootimg) seems to be broken on 8350, too?
I get a "your device is corrupted and will not boot" error, even though
I disabled vbmeta/vbmeta_system and performed the same steps described
in this commit message to dtbo/vendor_boot. It worked fine on
4.19-release SoCs without vendor_boot (8250, 6350), but it seems it
doesn't anymore.
Konrad
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 14/16] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (11 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 15/16] arm64: dts: qcom: sm8350-sagami: Configure remote processors Konrad Dybcio
` (2 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Based on current driver availability, add either nodes or comments regarding
peripherals connected via I2C/SPI.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
.../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
index b50f04ffee95..c44376aa0742 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
@@ -75,6 +75,93 @@ ramoops@ffc00000 {
};
};
+&i2c1 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ /* Some subset of SONY IMX663 camera sensor @ 38 */
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Richwave RTC6226 FM Radio Receiver @ 64 */
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Samsung Touchscreen (needs I2C GPI DMA) @ 48 */
+};
+
+&i2c11 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ cs35l41_l: cs35l41@40 {
+ compatible = "cirrus,cs35l41";
+ reg = <0x40>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <36 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ cirrus,boost-peak-milliamp = <4000>;
+ cirrus,boost-ind-nanohenry = <1000>;
+ cirrus,boost-cap-microfarad = <15>;
+ cirrus,asp-sdout-hiz = <3>;
+ cirrus,gpio2-src-select = <2>;
+ cirrus,gpio2-output-enable;
+ #sound-dai-cells = <1>;
+ };
+
+ cs35l41_r: cs35l41@41 {
+ compatible = "cirrus,cs35l41";
+ reg = <0x41>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <36 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ cirrus,boost-peak-milliamp = <4000>;
+ cirrus,boost-ind-nanohenry = <1000>;
+ cirrus,boost-cap-microfarad = <15>;
+ cirrus,asp-sdout-hiz = <3>;
+ cirrus,gpio2-src-select = <2>;
+ cirrus,gpio2-output-enable;
+ #sound-dai-cells = <1>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+ /* Clock frequency was not specified downstream, let's park it to 100 KHz */
+ clock-frequency = <100000>;
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c13 {
+ status = "okay";
+ /* Clock frequency was not specified downstream, let's park it to 100 KHz */
+ clock-frequency = <100000>;
+
+ /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */
+ /* Dialog SLG51000 CMIC @ 75 */
+};
+
+&i2c15 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* NXP SN1X0 NFC @ 28 */
+};
+
+&i2c17 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */
+};
+
&pmk8350_rtc {
status = "okay";
};
@@ -100,8 +187,22 @@ &qupv3_id_2 {
status = "okay";
};
+&spi14 {
+ status = "okay";
+
+ /* NXP SN1X0 NFC Secure Element @ 0 */
+};
+
&tlmm {
gpio-reserved-ranges = <44 4>;
+
+ ts_int_default: ts-int-default {
+ pin = "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
};
/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 15/16] arm64: dts: qcom: sm8350-sagami: Configure remote processors
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (12 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 14/16] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-14 1:27 ` [PATCH 16/16] arm64: dts: qcom: sm8350: Add LLCC node Konrad Dybcio
2021-11-20 23:55 ` [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Bjorn Andersson
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Configure ADSP, CDSP, MPSS, SLPI and IPA on SoMC Sagami.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
.../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
index c44376aa0742..90b13cbe2fa6 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
@@ -75,6 +75,16 @@ ramoops@ffc00000 {
};
};
+&adsp {
+ status = "okay";
+ firmware-name = "qcom/adsp.mbn";
+};
+
+&cdsp {
+ status = "okay";
+ firmware-name = "qcom/cdsp.mbn";
+};
+
&i2c1 {
status = "okay";
clock-frequency = <1000000>;
@@ -162,6 +172,17 @@ &i2c17 {
/* Cirrus Logic CS40L25A boosted haptics driver @ 40 */
};
+&ipa {
+ status = "okay";
+ memory-region = <&pil_ipa_fw_mem>;
+ firmware-name = "qcom/ipa_fws.mbn";
+};
+
+&mpss {
+ status = "okay";
+ firmware-name = "qcom/modem.mbn";
+};
+
&pmk8350_rtc {
status = "okay";
};
@@ -187,6 +208,11 @@ &qupv3_id_2 {
status = "okay";
};
+&slpi {
+ status = "okay";
+ firmware-name = "qcom/slpi.mbn";
+};
+
&spi14 {
status = "okay";
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 16/16] arm64: dts: qcom: sm8350: Add LLCC node
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (13 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 15/16] arm64: dts: qcom: sm8350-sagami: Configure remote processors Konrad Dybcio
@ 2021-11-14 1:27 ` Konrad Dybcio
2021-11-20 23:55 ` [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Bjorn Andersson
15 siblings, 0 replies; 24+ messages in thread
From: Konrad Dybcio @ 2021-11-14 1:27 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Configure the Last-Level Cache Controller for SM8350.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0ea735d0df49..7323ed74f41a 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2232,6 +2232,12 @@ gem_noc: interconnect@9100000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ system-cache-controller@9200000 {
+ compatible = "qcom,sm8350-llcc";
+ reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.33.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI
2021-11-14 1:27 [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Konrad Dybcio
` (14 preceding siblings ...)
2021-11-14 1:27 ` [PATCH 16/16] arm64: dts: qcom: sm8350: Add LLCC node Konrad Dybcio
@ 2021-11-20 23:55 ` Bjorn Andersson
15 siblings, 0 replies; 24+ messages in thread
From: Bjorn Andersson @ 2021-11-20 23:55 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: linux-arm-msm, linux-kernel, devicetree, martin.botka, Kees Cook,
Rob Herring, Andy Gross, jamipkettunen, Tony Luck,
angelogioacchino.delregno, Colin Cross, marijn.suijten,
Anton Vorontsov
On Sun, 14 Nov 2021 02:27:40 +0100, Konrad Dybcio wrote:
> Almost any board that boots and has a way to interact with it
> (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup)
> needs to set some GPIOs, so it makes no sense to include gpio.h separately
> each time. Hence move it to SoC DTSI.
>
>
Applied, thanks!
[01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI
commit: f0360a7c1742681c390f2d94bb876ce80a8012b1
[02/16] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2
commit: e84d04a2b221153b88f644d98b5902c3705f5348
[03/16] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3
commit: f4d4ca9f3934844b99af289cf38d4892c73f683e
[04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer
commit: ed9500c1df59437856d43e657f185fb1eb5d817d
[05/16] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts
commit: 9e7f7b65c7f04c5cfda97d6bd0d452a49e60f24e
[06/16] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name
commit: f52dd33943ca5f84ae76890f352f6d9e12512c3f
[07/16] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage
commit: 2dab7aac493df72f57498044cb38ca0a6c18e7e1
[08/16] arm64: dts: qcom: sm8350: Describe GCC dependency clocks
commit: 9ea9eb36b3c046fc48e737db4de69f7acd12f9be
[09/16] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs
commit: cf03cd7e12bdb43d624dbd55d8467b29e9b608c2
[10/16] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs
commit: 8934535531c875e6ec67876905982a44e8306c1c
[11/16] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs
commit: 98374e6925b88cfc4e528faed230a835f91a576d
[12/16] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs
commit: 9bc2c8fea55c12d3720a80a59f99fdf68b8de773
[13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III
commit: c2721b0c23d975c73bce68d40435d66fbab19047
[14/16] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes
commit: 1209e9246632d93f557c651110533bf44f8335f3
[15/16] arm64: dts: qcom: sm8350-sagami: Configure remote processors
commit: ce2762aec7378892d398b784a4bfd4856dd71043
[16/16] arm64: dts: qcom: sm8350: Add LLCC node
commit: 9ac8999e8d6c05826664a61bc89509824f45621d
Best regards,
--
Bjorn Andersson <bjorn.andersson@linaro.org>
^ permalink raw reply [flat|nested] 24+ messages in thread