From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: airlied@linux.ie, tao.zhou1@amd.com,
dri-devel@lists.freedesktop.org, ray.huang@amd.com,
Likun.Gao@amd.com, Sasha Levin <sashal@kernel.org>,
James.Zhu@amd.com, aaron.liu@amd.com,
amd-gfx@lists.freedesktop.org, ChengZhe.Liu@amd.com,
veerabadhran.gopalakrishnan@amd.com, kenneth.feng@amd.com,
Lijo Lazar <lijo.lazar@amd.com>,
Bokun Zhang <bokun.zhang@amd.com>,
le.ma@amd.com, evan.quan@amd.com, john.clements@amd.com,
Jack.Gui@amd.com, Felix Kuehling <Felix.Kuehling@amd.com>,
Xinhui.Pan@amd.com, daniel@ffwll.ch,
Alex Deucher <alexander.deucher@amd.com>,
candice.li@amd.com, leo.liu@amd.com, christian.koenig@amd.com,
Hawking.Zhang@amd.com
Subject: [PATCH AUTOSEL 5.15 55/68] drm/amdgpu: Fix MMIO HDP flush on SRIOV
Date: Tue, 30 Nov 2021 09:46:51 -0500 [thread overview]
Message-ID: <20211130144707.944580-55-sashal@kernel.org> (raw)
In-Reply-To: <20211130144707.944580-1-sashal@kernel.org>
From: Felix Kuehling <Felix.Kuehling@amd.com>
[ Upstream commit d3a21f7e353dc8d6939383578f3bd45b4ae3a946 ]
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset
to the fixed address of the VF register for hdp_v*_flush_hdp.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++---
7 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index b184b656b9b6b..a76b5e47e7cbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -328,6 +328,10 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 0d2d629e2d6a2..4bbacf1be25a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,6 +276,10 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CI_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 3c00666a13e16..37a4039fdfc53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -273,7 +273,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 8f2a315e7c73c..3444332ea1104 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -371,6 +371,10 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
}
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f50045cebd44c..9b3f64971a321 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -344,7 +344,9 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 01efda4398e56..b739166b242a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1034,8 +1034,10 @@ static int nv_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &nv_pcie_rreg;
@@ -1333,7 +1335,7 @@ static int nv_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
nv_enable_doorbell_aperture(adev, true);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0fc97c364fd76..a3361cd68411a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1136,8 +1136,10 @@ static int soc15_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &soc15_pcie_rreg;
@@ -1446,7 +1448,7 @@ static int soc15_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
--
2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: airlied@linux.ie, tao.zhou1@amd.com,
dri-devel@lists.freedesktop.org, ray.huang@amd.com,
Likun.Gao@amd.com, Sasha Levin <sashal@kernel.org>,
James.Zhu@amd.com, aaron.liu@amd.com,
amd-gfx@lists.freedesktop.org, ChengZhe.Liu@amd.com,
veerabadhran.gopalakrishnan@amd.com, kenneth.feng@amd.com,
Lijo Lazar <lijo.lazar@amd.com>,
Bokun Zhang <bokun.zhang@amd.com>,
le.ma@amd.com, evan.quan@amd.com, john.clements@amd.com,
Jack.Gui@amd.com, Felix Kuehling <Felix.Kuehling@amd.com>,
Xinhui.Pan@amd.com, Alex Deucher <alexander.deucher@amd.com>,
candice.li@amd.com, leo.liu@amd.com, christian.koenig@amd.com,
Hawking.Zhang@amd.com
Subject: [PATCH AUTOSEL 5.15 55/68] drm/amdgpu: Fix MMIO HDP flush on SRIOV
Date: Tue, 30 Nov 2021 09:46:51 -0500 [thread overview]
Message-ID: <20211130144707.944580-55-sashal@kernel.org> (raw)
In-Reply-To: <20211130144707.944580-1-sashal@kernel.org>
From: Felix Kuehling <Felix.Kuehling@amd.com>
[ Upstream commit d3a21f7e353dc8d6939383578f3bd45b4ae3a946 ]
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset
to the fixed address of the VF register for hdp_v*_flush_hdp.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++---
7 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index b184b656b9b6b..a76b5e47e7cbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -328,6 +328,10 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 0d2d629e2d6a2..4bbacf1be25a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,6 +276,10 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CI_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 3c00666a13e16..37a4039fdfc53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -273,7 +273,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 8f2a315e7c73c..3444332ea1104 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -371,6 +371,10 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
}
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f50045cebd44c..9b3f64971a321 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -344,7 +344,9 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 01efda4398e56..b739166b242a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1034,8 +1034,10 @@ static int nv_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &nv_pcie_rreg;
@@ -1333,7 +1335,7 @@ static int nv_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
nv_enable_doorbell_aperture(adev, true);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0fc97c364fd76..a3361cd68411a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1136,8 +1136,10 @@ static int soc15_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &soc15_pcie_rreg;
@@ -1446,7 +1448,7 @@ static int soc15_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
--
2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Felix Kuehling <Felix.Kuehling@amd.com>,
Bokun Zhang <bokun.zhang@amd.com>,
Lijo Lazar <lijo.lazar@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>,
christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie,
daniel@ffwll.ch, evan.quan@amd.com, Likun.Gao@amd.com,
Hawking.Zhang@amd.com, ChengZhe.Liu@amd.com,
kenneth.feng@amd.com, ray.huang@amd.com, aaron.liu@amd.com,
john.clements@amd.com, le.ma@amd.com, James.Zhu@amd.com,
candice.li@amd.com, tao.zhou1@amd.com, Jack.Gui@amd.com,
veerabadhran.gopalakrishnan@amd.com, leo.liu@amd.com,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [PATCH AUTOSEL 5.15 55/68] drm/amdgpu: Fix MMIO HDP flush on SRIOV
Date: Tue, 30 Nov 2021 09:46:51 -0500 [thread overview]
Message-ID: <20211130144707.944580-55-sashal@kernel.org> (raw)
In-Reply-To: <20211130144707.944580-1-sashal@kernel.org>
From: Felix Kuehling <Felix.Kuehling@amd.com>
[ Upstream commit d3a21f7e353dc8d6939383578f3bd45b4ae3a946 ]
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset
to the fixed address of the VF register for hdp_v*_flush_hdp.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++---
7 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index b184b656b9b6b..a76b5e47e7cbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -328,6 +328,10 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 0d2d629e2d6a2..4bbacf1be25a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,6 +276,10 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE(smnPCIE_CI_CNTL, data);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 3c00666a13e16..37a4039fdfc53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -273,7 +273,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 8f2a315e7c73c..3444332ea1104 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -371,6 +371,10 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
}
+
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f50045cebd44c..9b3f64971a321 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -344,7 +344,9 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
{
-
+ if (amdgpu_sriov_vf(adev))
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
}
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 01efda4398e56..b739166b242a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1034,8 +1034,10 @@ static int nv_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &nv_pcie_rreg;
@@ -1333,7 +1335,7 @@ static int nv_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
nv_enable_doorbell_aperture(adev, true);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0fc97c364fd76..a3361cd68411a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1136,8 +1136,10 @@ static int soc15_common_early_init(void *handle)
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ }
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = &soc15_pcie_rreg;
@@ -1446,7 +1448,7 @@ static int soc15_common_hw_init(void *handle)
* for the purpose of expose those registers
* to process space
*/
- if (adev->nbio.funcs->remap_hdp_registers)
+ if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
--
2.33.0
next prev parent reply other threads:[~2021-11-30 14:57 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 14:45 [PATCH AUTOSEL 5.15 01/68] ASoC: mediatek: mt8173-rt5650: Rename Speaker control to Ext Spk Sasha Levin
2021-11-30 14:45 ` Sasha Levin
2021-11-30 14:45 ` Sasha Levin
2021-11-30 14:45 ` Sasha Levin
2021-11-30 14:45 ` [PATCH AUTOSEL 5.15 02/68] ASoC: Intel: sof_sdw: Add support for SKU 0AF3 product Sasha Levin
2021-11-30 14:45 ` Sasha Levin
2021-11-30 14:45 ` [PATCH AUTOSEL 5.15 03/68] ASoC: Intel: soc-acpi: add SKU 0AF3 SoundWire configuration Sasha Levin
2021-11-30 14:45 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 04/68] ASoC: Intel: sof_sdw: Add support for SKU 0B00 and 0B01 products Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 05/68] ASoC: Intel: sof_sdw: Add support for SKU 0B11 product Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 06/68] ASoC: Intel: sof_sdw: Add support for SKU 0B13 product Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 07/68] ASoC: Intel: soc-acpi: add SKU 0B13 SoundWire configuration Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 08/68] ASoC: Intel: sof_sdw: Add support for SKU 0B29 product Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 09/68] ASoC: Intel: soc-acpi: add SKU 0B29 SoundWire configuration Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 10/68] ASoC: Intel: sof_sdw: Add support for SKU 0B12 product Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 11/68] ASoC: rt5682: Avoid the unexpected IRQ event during going to suspend Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 12/68] ASoC: rt5682: Re-detect the combo jack after resuming Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 13/68] ASoC: mediatek: mt8173: Fix debugfs registration for components Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 14/68] ASoC: qdsp6: q6adm: improve error reporting Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 15/68] ASoC: qdsp6: q6routing: validate port id before setting up route Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 16/68] xen/privcmd: make option visible in Kconfig Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 17/68] NFSv4.1: handle NFS4ERR_NOSPC by CREATE_SESSION Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 18/68] scsi: ufs: ufshpb: Fix warning in ufshpb_set_hpb_read_to_upiu() Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 19/68] scsi: scsi_debug: Fix type in min_t to avoid stack OOB Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 20/68] scsi: ufs: ufs-mediatek: Add put_device() after of_find_device_by_node() Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 21/68] atlantic: fix double-free in aq_ring_tx_clean Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 22/68] stmmac_pci: Fix underflow size in stmmac_rx Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 23/68] HID: ft260: fix i2c probing for hwmon devices Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 24/68] HID: Ignore battery for Elan touchscreen on HP Envy X360 15-eu0xxx Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 25/68] HID: multitouch: Fix Iiyama ProLite T1931SAW (0eef:0001 again!) Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 26/68] parisc: Increase FRAME_WARN to 2048 bytes on parisc Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 27/68] parisc: Provide an extru_safe() macro to extract unsigned bits Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 28/68] parisc: Fix extraction of hash lock bits in syscall.S Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 29/68] parisc: Convert PTE lookup to use extru_safe() macro Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 30/68] selftests/tc-testing: match any qdisc type Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 31/68] selftests/tc-testings: Be compatible with newer tc output Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 32/68] block: avoid to touch unloaded module instance when opening bdev Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 33/68] scsi: scsi_debug: Sanity check block descriptor length in resp_mode_select() Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 34/68] locking/rwsem: Optimize down_read_trylock() under highly contended case Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 35/68] i2c: i801: Fix interrupt storm from SMB_ALERT signal Sasha Levin
2021-12-03 8:30 ` Jean Delvare
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 36/68] mmc: spi: Add device-tree SPI IDs Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 37/68] net: chelsio: cxgb4vf: Fix an error code in cxgb4vf_pci_probe() Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 38/68] cifs: populate server_hostname for extra channels Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 39/68] smb2: clarify rc initialization in smb2_reconnect Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 40/68] nvmet-tcp: fix a race condition between release_queue and io_work Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 41/68] nvmet-tcp: add an helper to free the cmd buffers Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 42/68] nvmet-tcp: fix memory leak when performing a controller reset Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 43/68] nvme-tcp: validate R2T PDU in nvme_tcp_handle_r2t() Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 44/68] nvme-tcp: fix memory leak when freeing a queue Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 45/68] nvme-pci: add NO APST quirk for Kioxia device Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 46/68] nvme-fabrics: ignore invalid fast_io_fail_tmo values Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 47/68] nvme: fix write zeroes pi Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 48/68] xen: add "not_essential" flag to struct xenbus_driver Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 49/68] xen: flag xen_drm_front to be not essential for system boot Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 50/68] xen: flag hvc_xen " Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 51/68] xen: flag pvcalls-front " Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 52/68] xen: flag xen_snd_front " Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 53/68] x86/boot: Mark prepare_command_line() __init Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 54/68] PM: hibernate: Fix snapshot partial write lengths Sasha Levin
2021-11-30 14:46 ` Sasha Levin [this message]
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 55/68] drm/amdgpu: Fix MMIO HDP flush on SRIOV Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 56/68] drm/amdgpu: Fix double free of dmabuf Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 57/68] drm/amd/display: Fixed DSC would not PG after removing DSC stream Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 58/68] drm/amdkfd: handle VMA remove race Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 59/68] drm/amdgpu: fix byteorder error in amdgpu discovery Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 60/68] drm/amd/display: update bios scratch when setting backlight Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 61/68] vhost-vdpa: clean irqs before reseting vdpa device Sasha Levin
2021-11-30 14:46 ` Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 62/68] MIPS: boot/compressed/: add __ashldi3 to target for ZSTD compression Sasha Levin
2021-11-30 14:46 ` [PATCH AUTOSEL 5.15 63/68] nfc: virtual_ncidev: change default device permissions Sasha Levin
2021-11-30 14:47 ` [PATCH AUTOSEL 5.15 64/68] net: qed: fix the array may be out of bound Sasha Levin
2021-11-30 14:47 ` [PATCH AUTOSEL 5.15 65/68] net: mscc: ocelot: create a function that replaces an existing VCAP filter Sasha Levin
2021-12-04 14:46 ` Vladimir Oltean
2021-11-30 14:47 ` [PATCH AUTOSEL 5.15 66/68] net: ptp: add a definition for the UDP port for IEEE 1588 general messages Sasha Levin
2021-11-30 14:47 ` [PATCH AUTOSEL 5.15 67/68] io_uring: Fix undefined-behaviour in io_issue_sqe Sasha Levin
2021-11-30 14:47 ` [PATCH AUTOSEL 5.15 68/68] fs: ntfs: Limit NTFS_RW to page sizes smaller than 64k Sasha Levin
2021-11-30 15:16 ` [PATCH AUTOSEL 5.15 01/68] ASoC: mediatek: mt8173-rt5650: Rename Speaker control to Ext Spk Mark Brown
2021-11-30 15:16 ` Mark Brown
2021-11-30 15:16 ` Mark Brown
2021-11-30 15:16 ` Mark Brown
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