From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH v2 02/14] cxl: Introduce endpoint decoders
Date: Wed, 1 Dec 2021 20:37:38 -0800 [thread overview]
Message-ID: <20211202043750.3501494-3-ben.widawsky@intel.com> (raw)
In-Reply-To: <20211202043750.3501494-1-ben.widawsky@intel.com>
Endpoints have decoders too. It is useful to share the same
infrastructure from cxl_core. Endpoints do not have dports (downstream
targets), only the underlying physical medium. As a result, some special
casing is needed.
There is no functional change introduced yet as endpoints don't actually
enumerate decoders yet.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
Dan brought up having an endpoint specific API for adding decoders.
Ultimately I didn't see value in doing this, so it's not here. I'm open
for discussion. Until the final patch in the series, there isn't much
reason to have it.
---
drivers/cxl/core/bus.c | 54 ++++++++++++++++++++++++++++++++++++------
drivers/cxl/cxl.h | 1 +
2 files changed, 48 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index 2f72087846e3..2bf9c0704a70 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -187,6 +187,12 @@ static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = {
NULL,
};
+static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {
+ &cxl_decoder_base_attribute_group,
+ &cxl_base_attribute_group,
+ NULL,
+};
+
static void cxl_decoder_release(struct device *dev)
{
struct cxl_decoder *cxld = to_cxl_decoder(dev);
@@ -196,6 +202,12 @@ static void cxl_decoder_release(struct device *dev)
kfree(cxld);
}
+static const struct device_type cxl_decoder_endpoint_type = {
+ .name = "cxl_decoder_endpoint",
+ .release = cxl_decoder_release,
+ .groups = cxl_decoder_endpoint_attribute_groups,
+};
+
static const struct device_type cxl_decoder_switch_type = {
.name = "cxl_decoder_switch",
.release = cxl_decoder_release,
@@ -208,6 +220,11 @@ static const struct device_type cxl_decoder_root_type = {
.groups = cxl_decoder_root_attribute_groups,
};
+static bool is_endpoint_decoder(struct device *dev)
+{
+ return dev->type == &cxl_decoder_endpoint_type;
+}
+
bool is_root_decoder(struct device *dev)
{
return dev->type == &cxl_decoder_root_type;
@@ -499,7 +516,9 @@ static int decoder_populate_targets(struct cxl_decoder *cxld,
* cxl_decoder_alloc - Allocate a new CXL decoder
* @port: owning port of this decoder
* @nr_targets: downstream targets accessible by this decoder. All upstream
- * ports and root ports must have at least 1 target.
+ * ports and root ports must have at least 1 target. Endpoint
+ * devices will have 0 targets. Callers wishing to register an
+ * endpoint device should specify 0.
*
* A port should contain one or more decoders. Each of those decoders enable
* some address space for CXL.mem utilization. A decoder is expected to be
@@ -516,7 +535,7 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
struct device *dev;
int rc = 0;
- if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets == 0)
+ if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
return ERR_PTR(-EINVAL);
cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
@@ -583,6 +602,24 @@ struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
}
EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
+/**
+ * cxl_endpoint_decoder_alloc - Allocate an endpoint decoder
+ * @port: owning port of this decoder
+ *
+ * Return: A new cxl decoder to be registered by cxl_decoder_add()
+ */
+struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
+{
+ struct cxl_decoder *cxld;
+
+ cxld = cxl_decoder_alloc(port, 0);
+ if (!IS_ERR(cxld))
+ cxld->dev.type = &cxl_decoder_endpoint_type;
+
+ return cxld;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
+
/**
* cxl_decoder_add - Add a decoder with targets
* @cxld: The cxl decoder allocated by cxl_decoder_alloc()
@@ -614,12 +651,15 @@ int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
if (cxld->interleave_ways < 1)
return -EINVAL;
- port = to_cxl_port(cxld->dev.parent);
- rc = decoder_populate_targets(cxld, port, target_map);
- if (rc)
- return rc;
-
dev = &cxld->dev;
+
+ port = to_cxl_port(cxld->dev.parent);
+ if (!is_endpoint_decoder(dev)) {
+ rc = decoder_populate_targets(cxld, port, target_map);
+ if (rc)
+ return rc;
+ }
+
rc = dev_set_name(dev, "decoder%d.%d", port->id, cxld->id);
if (rc)
return rc;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index a036594ec5b3..9b3904788762 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -292,6 +292,7 @@ struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
unsigned int nr_targets);
struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
unsigned int nr_targets);
+struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
--
2.34.1
next prev parent reply other threads:[~2021-12-02 4:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 4:37 [PATCH v2 00/14] Add drivers for CXL ports and mem devices Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 01/14] cxl/core: Add, document, and tighten up decoder APIs Ben Widawsky
2021-12-06 10:51 ` Jonathan Cameron
2021-12-02 4:37 ` Ben Widawsky [this message]
2021-12-02 4:37 ` [PATCH v2 03/14] cxl/core: Move target population locking to caller Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 04/14] cxl: Introduce topology host registration Ben Widawsky
2021-12-02 5:58 ` Dan Williams
2021-12-03 21:06 ` Dan Williams
2021-12-04 3:21 ` Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 05/14] cxl/core: Store global list of root ports Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 06/14] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 07/14] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 08/14] cxl/pci: Implement wait for media active Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 09/14] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 10/14] cxl: Make passthrough decoder init implicit Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 11/14] cxl/port: Introduce a port driver Ben Widawsky
2021-12-02 6:36 ` Dan Williams
2021-12-02 4:37 ` [PATCH v2 12/14] cxl: Unify port enumeration for decoders Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 13/14] cxl/port: Cleanup adding passthrough decoders Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 14/14] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-12-04 4:07 ` Dan Williams
2021-12-15 17:25 ` [PATCH v2 00/14] Add drivers for CXL ports and mem devices Jonathan Cameron
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