From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH v2 03/14] cxl/core: Move target population locking to caller
Date: Wed, 1 Dec 2021 20:37:39 -0800 [thread overview]
Message-ID: <20211202043750.3501494-4-ben.widawsky@intel.com> (raw)
In-Reply-To: <20211202043750.3501494-1-ben.widawsky@intel.com>
In preparation for a port driver that enumerates a descendant port +
decoder hierarchy, arrange for an unlocked version of cxl_decoder_add().
Otherwise a port-driver that adds a child decoder will deadlock on the
device_lock() in ->probe().
As a result of this change the device lock for the port is held for a
longer amount of time.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
Changes since v1:
- Fix kdoc describing the lock held (Dan)
---
drivers/cxl/core/bus.c | 61 +++++++++++++++++++++++++++++++-----------
drivers/cxl/cxl.h | 1 +
2 files changed, 47 insertions(+), 15 deletions(-)
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index 2bf9c0704a70..4bf355a3e396 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -487,28 +487,22 @@ static int decoder_populate_targets(struct cxl_decoder *cxld,
{
int rc = 0, i;
+ device_lock_assert(&port->dev);
+
if (!target_map)
return 0;
- device_lock(&port->dev);
- if (list_empty(&port->dports)) {
- rc = -EINVAL;
- goto out_unlock;
- }
+ if (list_empty(&port->dports))
+ return -EINVAL;
for (i = 0; i < cxld->nr_targets; i++) {
struct cxl_dport *dport = find_dport(port, target_map[i]);
- if (!dport) {
- rc = -ENXIO;
- goto out_unlock;
- }
+ if (!dport)
+ return -ENXIO;
cxld->target[i] = dport;
}
-out_unlock:
- device_unlock(&port->dev);
-
return rc;
}
@@ -621,7 +615,7 @@ struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
/**
- * cxl_decoder_add - Add a decoder with targets
+ * cxl_decoder_add_locked - Add a decoder with targets
* @cxld: The cxl decoder allocated by cxl_decoder_alloc()
* @target_map: A list of downstream ports that this decoder can direct memory
* traffic to. These numbers should correspond with the port number
@@ -631,12 +625,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
* is an endpoint device. A more awkward example is a hostbridge whose root
* ports get hot added (technically possible, though unlikely).
*
- * Context: Process context. Takes and releases the cxld's device lock.
+ * This is the locked variant of cxl_decoder_add().
+ *
+ * Context: Process context. Expects the device lock of the port that owns the
+ * @cxld to be held.
*
* Return: Negative error code if the decoder wasn't properly configured; else
* returns 0.
*/
-int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
+int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map)
{
struct cxl_port *port;
struct device *dev;
@@ -673,6 +670,40 @@ int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
return device_add(dev);
}
+EXPORT_SYMBOL_NS_GPL(cxl_decoder_add_locked, CXL);
+
+/**
+ * cxl_decoder_add - Add a decoder with targets
+ * @cxld: The cxl decoder allocated by cxl_decoder_alloc()
+ * @target_map: A list of downstream ports that this decoder can direct memory
+ * traffic to. These numbers should correspond with the port number
+ * in the PCIe Link Capabilities structure.
+ *
+ * This is the unlocked variant of cxl_decoder_add_locked().
+ * See cxl_decoder_add_locked().
+ *
+ * Context: Process context. Takes and releases the device lock of the port that
+ * owns the @cxld.
+ */
+int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
+{
+ struct cxl_port *port;
+ int rc;
+
+ if (WARN_ON_ONCE(!cxld))
+ return -EINVAL;
+
+ if (WARN_ON_ONCE(IS_ERR(cxld)))
+ return PTR_ERR(cxld);
+
+ port = to_cxl_port(cxld->dev.parent);
+
+ device_lock(&port->dev);
+ rc = cxl_decoder_add_locked(cxld, target_map);
+ device_unlock(&port->dev);
+
+ return rc;
+}
EXPORT_SYMBOL_NS_GPL(cxl_decoder_add, CXL);
static void cxld_unregister(void *dev)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 9b3904788762..762d8254c7c6 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -293,6 +293,7 @@ struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
unsigned int nr_targets);
struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
+int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
--
2.34.1
next prev parent reply other threads:[~2021-12-02 4:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 4:37 [PATCH v2 00/14] Add drivers for CXL ports and mem devices Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 01/14] cxl/core: Add, document, and tighten up decoder APIs Ben Widawsky
2021-12-06 10:51 ` Jonathan Cameron
2021-12-02 4:37 ` [PATCH v2 02/14] cxl: Introduce endpoint decoders Ben Widawsky
2021-12-02 4:37 ` Ben Widawsky [this message]
2021-12-02 4:37 ` [PATCH v2 04/14] cxl: Introduce topology host registration Ben Widawsky
2021-12-02 5:58 ` Dan Williams
2021-12-03 21:06 ` Dan Williams
2021-12-04 3:21 ` Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 05/14] cxl/core: Store global list of root ports Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 06/14] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 07/14] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 08/14] cxl/pci: Implement wait for media active Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 09/14] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 10/14] cxl: Make passthrough decoder init implicit Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 11/14] cxl/port: Introduce a port driver Ben Widawsky
2021-12-02 6:36 ` Dan Williams
2021-12-02 4:37 ` [PATCH v2 12/14] cxl: Unify port enumeration for decoders Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 13/14] cxl/port: Cleanup adding passthrough decoders Ben Widawsky
2021-12-02 4:37 ` [PATCH v2 14/14] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-12-04 4:07 ` Dan Williams
2021-12-15 17:25 ` [PATCH v2 00/14] Add drivers for CXL ports and mem devices Jonathan Cameron
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