Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2

["Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>]

On Fri, Dec 03, 2021 at 12:03:41PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 03, 2021 at 11:40:41AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
> >  1 file changed, 18 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0b45d1d61d0f..e1594f43bb1b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5245,9 +5245,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> >  			break;
> >  
> >  		rate = crtc_state->plane_data_rate[plane_id];
> > -		extra = min_t(u16, alloc_size,
> > -			      DIV64_U64_ROUND_UP(alloc_size * rate,
> > -						 total_data_rate));
> > +
> > +		if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
> 
> We should have a sensible function for this.

Agree, tbh was thinking about this as well.

> 
> > +			extra = 0;
> 
> Aren't we going to get the WARN(alloc_size != 0) if this
> is the only enabled plane?

Actually true as well, I remember I did get this warn when
I was testing it. 
I guess we shouldn't trigger WARN for that case then?

> 
> > +		} else {
> > +			extra = min_t(u16, alloc_size,
> > +				      DIV64_U64_ROUND_UP(alloc_size * rate,
> > +							 total_data_rate));
> > +		}
> > +
> >  		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> > @@ -5256,9 +5262,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> >  			break;
> >  
> >  		rate = crtc_state->uv_plane_data_rate[plane_id];
> > -		extra = min_t(u16, alloc_size,
> > -			      DIV64_U64_ROUND_UP(alloc_size * rate,
> > -						 total_data_rate));
> > +
> > +		if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
> > +			extra = 0;
> > +		} else {
> > +			extra = min_t(u16, alloc_size,
> > +				      DIV64_U64_ROUND_UP(alloc_size * rate,
> > +							 total_data_rate));
> > +		}
> > +
> >  		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel