From: Ramalingam C <ramalingam.c@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
intel-gfx@lists.freedesktop.org, adrian.larumbe@collabora.com,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/migrate: fix offset calculation
Date: Fri, 3 Dec 2021 23:00:26 +0530 [thread overview]
Message-ID: <20211203173026.GB27873@intel.com> (raw)
In-Reply-To: <20211203122426.2859679-5-matthew.auld@intel.com>
On 2021-12-03 at 12:24:22 +0000, Matthew Auld wrote:
> Ensure we add the engine base only after we calculate the qword offset
> into the PTE window.
So we didn't hit this issue because we were always using the
engine->instance 0!?
Looks good to me
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index d553b76b1168..cb0bb3b94644 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -284,10 +284,10 @@ static int emit_pte(struct i915_request *rq,
> GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
>
> /* Compute the page directory offset for the target address range */
> - offset += (u64)rq->engine->instance << 32;
> offset >>= 12;
> offset *= sizeof(u64);
> offset += 2 * CHUNK_SZ;
> + offset += (u64)rq->engine->instance << 32;
>
> cs = intel_ring_begin(rq, 6);
> if (IS_ERR(cs))
> --
> 2.31.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: bob.beckett@collabora.com,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
intel-gfx@lists.freedesktop.org, adrian.larumbe@collabora.com,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 4/8] drm/i915/migrate: fix offset calculation
Date: Fri, 3 Dec 2021 23:00:26 +0530 [thread overview]
Message-ID: <20211203173026.GB27873@intel.com> (raw)
In-Reply-To: <20211203122426.2859679-5-matthew.auld@intel.com>
On 2021-12-03 at 12:24:22 +0000, Matthew Auld wrote:
> Ensure we add the engine base only after we calculate the qword offset
> into the PTE window.
So we didn't hit this issue because we were always using the
engine->instance 0!?
Looks good to me
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index d553b76b1168..cb0bb3b94644 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -284,10 +284,10 @@ static int emit_pte(struct i915_request *rq,
> GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
>
> /* Compute the page directory offset for the target address range */
> - offset += (u64)rq->engine->instance << 32;
> offset >>= 12;
> offset *= sizeof(u64);
> offset += 2 * CHUNK_SZ;
> + offset += (u64)rq->engine->instance << 32;
>
> cs = intel_ring_begin(rq, 6);
> if (IS_ERR(cs))
> --
> 2.31.1
>
next prev parent reply other threads:[~2021-12-03 17:27 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 12:24 [Intel-gfx] [PATCH v2 0/8] DG2 accelerated migration/clearing support Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 1/8] drm/i915/migrate: don't check the scratch page Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 16:38 ` [Intel-gfx] " Ramalingam C
2021-12-03 16:38 ` Ramalingam C
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 16:59 ` [Intel-gfx] " Ramalingam C
2021-12-03 16:59 ` Ramalingam C
2021-12-03 17:31 ` [Intel-gfx] " Matthew Auld
2021-12-03 17:31 ` Matthew Auld
2021-12-03 17:45 ` [Intel-gfx] " Ramalingam C
2021-12-03 17:45 ` Ramalingam C
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/gtt: add gtt mappable plumbing Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 17:25 ` [Intel-gfx] " Ramalingam C
2021-12-03 17:25 ` Ramalingam C
2021-12-03 17:38 ` [Intel-gfx] " Matthew Auld
2021-12-03 17:38 ` Matthew Auld
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/migrate: fix offset calculation Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 17:30 ` Ramalingam C [this message]
2021-12-03 17:30 ` Ramalingam C
2021-12-03 17:39 ` [Intel-gfx] " Matthew Auld
2021-12-03 17:39 ` Matthew Auld
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/migrate: fix length calculation Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 17:36 ` [Intel-gfx] " Ramalingam C
2021-12-03 17:36 ` Ramalingam C
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/selftests: handle object rounding Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 17:40 ` [Intel-gfx] " Ramalingam C
2021-12-03 17:40 ` Ramalingam C
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/migrate: add acceleration support for DG2 Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 12:24 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/migrate: turn on acceleration " Matthew Auld
2021-12-03 12:24 ` Matthew Auld
2021-12-03 14:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 accelerated migration/clearing support Patchwork
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