[PATCH v3 0/3] drm/vc4: Support for 30 bits YUV formats

[PATCH v3 0/3] drm/vc4: Support for 30 bits YUV formats

[Maxime Ripard]

Hi,

Here are a few patches adding support for the P030 and the BT709 and BT2020
colorspaces.

Let me know what you think,
Maxime

Changes from v2:
  - Fixed Dave email address
  - Fixed a typo in the first patch commit log

Changes from v1:
 - Reworded the format description
 - Fixed use before initialisation

Dave Stevenson (3):
  drm/fourcc: Add packed 10bit YUV 4:2:0 format
  drm/vc4: plane: Add support for DRM_FORMAT_P030
  drm/vc4: plane: Add support for YUV color encodings and ranges

 drivers/gpu/drm/drm_fourcc.c    |   3 +
 drivers/gpu/drm/vc4/vc4_plane.c | 199 ++++++++++++++++++++++++++------
 drivers/gpu/drm/vc4/vc4_regs.h  |  19 ++-
 include/uapi/drm/drm_fourcc.h   |  11 ++
 4 files changed, 193 insertions(+), 39 deletions(-)

-- 
2.33.1

[PATCH v3 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format

[Maxime Ripard]

From: Dave Stevenson <dave.stevenson@raspberrypi.com>

Adds a format that is 3 10bit YUV 4:2:0 samples packed into
a 32bit word (with 2 spare bits).

Supported on Broadcom BCM2711 chips.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/drm_fourcc.c  |  3 +++
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 25837b1d6639..07741b678798 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -269,6 +269,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
 		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
 		  .vsub = 0, .is_yuv = true },
+		{ .format = DRM_FORMAT_P030,            .depth = 0,  .num_planes = 2,
+		  .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
+		  .hsub = 2, .vsub = 2, .is_yuv = true},
 	};
 
 	unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..fc0c1454d275 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -314,6 +314,13 @@ extern "C" {
  */
 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
 
+/* 2 plane YCbCr420.
+ * 3 10 bit components and 2 padding bits packed into 4 bytes.
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
+ */
+#define DRM_FORMAT_P030		fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
+
 /* 3 plane non-subsampled (444) YCbCr
  * 16 bits per component, but only 10 bits are used and 6 bits are padded
  * index 0: Y plane, [15:0] Y:x [10:6] little endian
@@ -854,6 +861,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  * and UV.  Some SAND-using hardware stores UV in a separate tiled
  * image from Y to reduce the column height, which is not supported
  * with these modifiers.
+ *
+ * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
+ * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
+ * wide, but as this is a 10 bpp format that translates to 96 pixels.
  */
 
 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
-- 
2.33.1

[PATCH v3 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030

[Maxime Ripard]

From: Dave Stevenson <dave.stevenson@raspberrypi.com>

The P030 format, used with the DRM_FORMAT_MOD_BROADCOM_SAND128 modifier,
is a format output by the video decoder on the BCM2711.

Add native support to the KMS planes for that format.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_plane.c | 128 ++++++++++++++++++++++++--------
 1 file changed, 97 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index ac761c683663..18627b240a55 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -33,6 +33,7 @@ static const struct hvs_format {
 	u32 hvs; /* HVS_FORMAT_* */
 	u32 pixel_order;
 	u32 pixel_order_hvs5;
+	bool hvs5_only;
 } hvs_formats[] = {
 	{
 		.drm = DRM_FORMAT_XRGB8888,
@@ -128,6 +129,12 @@ static const struct hvs_format {
 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 	},
+	{
+		.drm = DRM_FORMAT_P030,
+		.hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,
+		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
+		.hvs5_only = true,
+	},
 };
 
 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
@@ -762,47 +769,91 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
 	case DRM_FORMAT_MOD_BROADCOM_SAND128:
 	case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 		uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
-		u32 tile_w, tile, x_off, pix_per_tile;
-
-		hvs_format = HVS_PIXEL_FORMAT_H264;
-
-		switch (base_format_mod) {
-		case DRM_FORMAT_MOD_BROADCOM_SAND64:
-			tiling = SCALER_CTL0_TILING_64B;
-			tile_w = 64;
-			break;
-		case DRM_FORMAT_MOD_BROADCOM_SAND128:
-			tiling = SCALER_CTL0_TILING_128B;
-			tile_w = 128;
-			break;
-		case DRM_FORMAT_MOD_BROADCOM_SAND256:
-			tiling = SCALER_CTL0_TILING_256B_OR_T;
-			tile_w = 256;
-			break;
-		default:
-			break;
-		}
 
 		if (param > SCALER_TILE_HEIGHT_MASK) {
-			DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
+			DRM_DEBUG_KMS("SAND height too large (%d)\n",
+				      param);
 			return -EINVAL;
 		}
 
-		pix_per_tile = tile_w / fb->format->cpp[0];
-		tile = vc4_state->src_x / pix_per_tile;
-		x_off = vc4_state->src_x % pix_per_tile;
+		if (fb->format->format == DRM_FORMAT_P030) {
+			hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
+			tiling = SCALER_CTL0_TILING_128B;
+		} else {
+			hvs_format = HVS_PIXEL_FORMAT_H264;
+
+			switch (base_format_mod) {
+			case DRM_FORMAT_MOD_BROADCOM_SAND64:
+				tiling = SCALER_CTL0_TILING_64B;
+				break;
+			case DRM_FORMAT_MOD_BROADCOM_SAND128:
+				tiling = SCALER_CTL0_TILING_128B;
+				break;
+			case DRM_FORMAT_MOD_BROADCOM_SAND256:
+				tiling = SCALER_CTL0_TILING_256B_OR_T;
+				break;
+			default:
+				return -EINVAL;
+				break;
+			}
+		}
 
 		/* Adjust the base pointer to the first pixel to be scanned
 		 * out.
+		 *
+		 * For P030, y_ptr [31:4] is the 128bit word for the start pixel
+		 * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
+		 * word that should be taken as the first pixel.
+		 * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
+		 * element within the 128bit word, eg for pixel 3 the value
+		 * should be 6.
 		 */
 		for (i = 0; i < num_planes; i++) {
+			u32 tile_w, tile, x_off, pix_per_tile;
+
+			if (fb->format->format == DRM_FORMAT_P030) {
+				/*
+				 * Spec says: bits [31:4] of the given address
+				 * should point to the 128-bit word containing
+				 * the desired starting pixel, and bits[3:0]
+				 * should be between 0 and 11, indicating which
+				 * of the 12-pixels in that 128-bit word is the
+				 * first pixel to be used
+				 */
+				u32 remaining_pixels = vc4_state->src_x % 96;
+				u32 aligned = remaining_pixels / 12;
+				u32 last_bits = remaining_pixels % 12;
+
+				x_off = aligned * 16 + last_bits;
+				tile_w = 128;
+				pix_per_tile = 96;
+			} else {
+				switch (base_format_mod) {
+				case DRM_FORMAT_MOD_BROADCOM_SAND64:
+					tile_w = 64;
+					break;
+				case DRM_FORMAT_MOD_BROADCOM_SAND128:
+					tile_w = 128;
+					break;
+				case DRM_FORMAT_MOD_BROADCOM_SAND256:
+					tile_w = 256;
+					break;
+				default:
+					break;
+				}
+				pix_per_tile = tile_w / fb->format->cpp[0];
+				x_off = (vc4_state->src_x % pix_per_tile) /
+					(i ? h_subsample : 1) *
+					fb->format->cpp[i];
+			}
+
+			tile = vc4_state->src_x / pix_per_tile;
+
 			vc4_state->offsets[i] += param * tile_w * tile;
 			vc4_state->offsets[i] += src_y /
 						 (i ? v_subsample : 1) *
 						 tile_w;
-			vc4_state->offsets[i] += x_off /
-						 (i ? h_subsample : 1) *
-						 fb->format->cpp[i];
+			vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
 		}
 
 		pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
@@ -955,7 +1006,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
 
 	/* Pitch word 1/2 */
 	for (i = 1; i < num_planes; i++) {
-		if (hvs_format != HVS_PIXEL_FORMAT_H264) {
+		if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
+		    hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
 			vc4_dlist_write(vc4_state,
 					VC4_SET_FIELD(fb->pitches[i],
 						      SCALER_SRC_PITCH));
@@ -1315,6 +1367,13 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
 		default:
 			return false;
 		}
+	case DRM_FORMAT_P030:
+		switch (fourcc_mod_broadcom_mod(modifier)) {
+		case DRM_FORMAT_MOD_BROADCOM_SAND128:
+			return true;
+		default:
+			return false;
+		}
 	case DRM_FORMAT_RGBX1010102:
 	case DRM_FORMAT_BGRX1010102:
 	case DRM_FORMAT_RGBA1010102:
@@ -1347,8 +1406,11 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 	struct drm_plane *plane = NULL;
 	struct vc4_plane *vc4_plane;
 	u32 formats[ARRAY_SIZE(hvs_formats)];
+	int num_formats = 0;
 	int ret = 0;
 	unsigned i;
+	bool hvs5 = of_device_is_compatible(dev->dev->of_node,
+					    "brcm,bcm2711-vc5");
 	static const uint64_t modifiers[] = {
 		DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 		DRM_FORMAT_MOD_BROADCOM_SAND128,
@@ -1363,13 +1425,17 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 	if (!vc4_plane)
 		return ERR_PTR(-ENOMEM);
 
-	for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
-		formats[i] = hvs_formats[i].drm;
+	for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
+		if (!hvs_formats[i].hvs5_only || hvs5) {
+			formats[num_formats] = hvs_formats[i].drm;
+			num_formats++;
+		}
+	}
 
 	plane = &vc4_plane->base;
 	ret = drm_universal_plane_init(dev, plane, 0,
 				       &vc4_plane_funcs,
-				       formats, ARRAY_SIZE(formats),
+				       formats, num_formats,
 				       modifiers, type, NULL);
 	if (ret)
 		return ERR_PTR(ret);
-- 
2.33.1

Re: [PATCH v3 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030

[kernel test robot]

Hi Maxime,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.16-rc5]
[cannot apply to anholt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-randconfig-r031-20211213 (https://download.01.org/0day-ci/archive/20211214/202112141058.EBPlKMSk-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project b6a2ddb6c8ac29412b1361810972e15221fa021c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/58b0d045769ea7e075fd1968a0da080b14b9ab70
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
        git checkout 58b0d045769ea7e075fd1968a0da080b14b9ab70
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/vc4/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/vc4/vc4_plane.c:841:5: warning: variable 'tile_w' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
                                   default:
                                   ^~~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:844:20: note: uninitialized use occurs here
                                   pix_per_tile = tile_w / fb->format->cpp[0];
                                                  ^~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:812:14: note: initialize the variable 'tile_w' to silence this warning
                           u32 tile_w, tile, x_off, pix_per_tile;
                                     ^
                                      = 0
   1 warning generated.


vim +/tile_w +841 drivers/gpu/drm/vc4/vc4_plane.c

   625	
   626	/* Writes out a full display list for an active plane to the plane's
   627	 * private dlist state.
   628	 */
   629	static int vc4_plane_mode_set(struct drm_plane *plane,
   630				      struct drm_plane_state *state)
   631	{
   632		struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
   633		struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
   634		struct drm_framebuffer *fb = state->fb;
   635		u32 ctl0_offset = vc4_state->dlist_count;
   636		const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
   637		u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
   638		int num_planes = fb->format->num_planes;
   639		u32 h_subsample = fb->format->hsub;
   640		u32 v_subsample = fb->format->vsub;
   641		bool mix_plane_alpha;
   642		bool covers_screen;
   643		u32 scl0, scl1, pitch0;
   644		u32 tiling, src_y;
   645		u32 hvs_format = format->hvs;
   646		unsigned int rotation;
   647		int ret, i;
   648	
   649		if (vc4_state->dlist_initialized)
   650			return 0;
   651	
   652		ret = vc4_plane_setup_clipping_and_scaling(state);
   653		if (ret)
   654			return ret;
   655	
   656		/* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
   657		 * and 4:4:4, scl1 should be set to scl0 so both channels of
   658		 * the scaler do the same thing.  For YUV, the Y plane needs
   659		 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
   660		 * the scl fields here.
   661		 */
   662		if (num_planes == 1) {
   663			scl0 = vc4_get_scl_field(state, 0);
   664			scl1 = scl0;
   665		} else {
   666			scl0 = vc4_get_scl_field(state, 1);
   667			scl1 = vc4_get_scl_field(state, 0);
   668		}
   669	
   670		rotation = drm_rotation_simplify(state->rotation,
   671						 DRM_MODE_ROTATE_0 |
   672						 DRM_MODE_REFLECT_X |
   673						 DRM_MODE_REFLECT_Y);
   674	
   675		/* We must point to the last line when Y reflection is enabled. */
   676		src_y = vc4_state->src_y;
   677		if (rotation & DRM_MODE_REFLECT_Y)
   678			src_y += vc4_state->src_h[0] - 1;
   679	
   680		switch (base_format_mod) {
   681		case DRM_FORMAT_MOD_LINEAR:
   682			tiling = SCALER_CTL0_TILING_LINEAR;
   683			pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
   684	
   685			/* Adjust the base pointer to the first pixel to be scanned
   686			 * out.
   687			 */
   688			for (i = 0; i < num_planes; i++) {
   689				vc4_state->offsets[i] += src_y /
   690							 (i ? v_subsample : 1) *
   691							 fb->pitches[i];
   692	
   693				vc4_state->offsets[i] += vc4_state->src_x /
   694							 (i ? h_subsample : 1) *
   695							 fb->format->cpp[i];
   696			}
   697	
   698			break;
   699	
   700		case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
   701			u32 tile_size_shift = 12; /* T tiles are 4kb */
   702			/* Whole-tile offsets, mostly for setting the pitch. */
   703			u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
   704			u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
   705			u32 tile_w_mask = (1 << tile_w_shift) - 1;
   706			/* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
   707			 * the height (in pixels) of a 4k tile.
   708			 */
   709			u32 tile_h_mask = (2 << tile_h_shift) - 1;
   710			/* For T-tiled, the FB pitch is "how many bytes from one row to
   711			 * the next, such that
   712			 *
   713			 *	pitch * tile_h == tile_size * tiles_per_row
   714			 */
   715			u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
   716			u32 tiles_l = vc4_state->src_x >> tile_w_shift;
   717			u32 tiles_r = tiles_w - tiles_l;
   718			u32 tiles_t = src_y >> tile_h_shift;
   719			/* Intra-tile offsets, which modify the base address (the
   720			 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
   721			 * base address).
   722			 */
   723			u32 tile_y = (src_y >> 4) & 1;
   724			u32 subtile_y = (src_y >> 2) & 3;
   725			u32 utile_y = src_y & 3;
   726			u32 x_off = vc4_state->src_x & tile_w_mask;
   727			u32 y_off = src_y & tile_h_mask;
   728	
   729			/* When Y reflection is requested we must set the
   730			 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
   731			 * after the initial one should be fetched in descending order,
   732			 * which makes sense since we start from the last line and go
   733			 * backward.
   734			 * Don't know why we need y_off = max_y_off - y_off, but it's
   735			 * definitely required (I guess it's also related to the "going
   736			 * backward" situation).
   737			 */
   738			if (rotation & DRM_MODE_REFLECT_Y) {
   739				y_off = tile_h_mask - y_off;
   740				pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
   741			} else {
   742				pitch0 = 0;
   743			}
   744	
   745			tiling = SCALER_CTL0_TILING_256B_OR_T;
   746			pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
   747				   VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
   748				   VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
   749				   VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
   750			vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
   751			vc4_state->offsets[0] += subtile_y << 8;
   752			vc4_state->offsets[0] += utile_y << 4;
   753	
   754			/* Rows of tiles alternate left-to-right and right-to-left. */
   755			if (tiles_t & 1) {
   756				pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
   757				vc4_state->offsets[0] += (tiles_w - tiles_l) <<
   758							 tile_size_shift;
   759				vc4_state->offsets[0] -= (1 + !tile_y) << 10;
   760			} else {
   761				vc4_state->offsets[0] += tiles_l << tile_size_shift;
   762				vc4_state->offsets[0] += tile_y << 10;
   763			}
   764	
   765			break;
   766		}
   767	
   768		case DRM_FORMAT_MOD_BROADCOM_SAND64:
   769		case DRM_FORMAT_MOD_BROADCOM_SAND128:
   770		case DRM_FORMAT_MOD_BROADCOM_SAND256: {
   771			uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
   772	
   773			if (param > SCALER_TILE_HEIGHT_MASK) {
   774				DRM_DEBUG_KMS("SAND height too large (%d)\n",
   775					      param);
   776				return -EINVAL;
   777			}
   778	
   779			if (fb->format->format == DRM_FORMAT_P030) {
   780				hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
   781				tiling = SCALER_CTL0_TILING_128B;
   782			} else {
   783				hvs_format = HVS_PIXEL_FORMAT_H264;
   784	
   785				switch (base_format_mod) {
   786				case DRM_FORMAT_MOD_BROADCOM_SAND64:
   787					tiling = SCALER_CTL0_TILING_64B;
   788					break;
   789				case DRM_FORMAT_MOD_BROADCOM_SAND128:
   790					tiling = SCALER_CTL0_TILING_128B;
   791					break;
   792				case DRM_FORMAT_MOD_BROADCOM_SAND256:
   793					tiling = SCALER_CTL0_TILING_256B_OR_T;
   794					break;
   795				default:
   796					return -EINVAL;
   797					break;
   798				}
   799			}
   800	
   801			/* Adjust the base pointer to the first pixel to be scanned
   802			 * out.
   803			 *
   804			 * For P030, y_ptr [31:4] is the 128bit word for the start pixel
   805			 * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
   806			 * word that should be taken as the first pixel.
   807			 * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
   808			 * element within the 128bit word, eg for pixel 3 the value
   809			 * should be 6.
   810			 */
   811			for (i = 0; i < num_planes; i++) {
   812				u32 tile_w, tile, x_off, pix_per_tile;
   813	
   814				if (fb->format->format == DRM_FORMAT_P030) {
   815					/*
   816					 * Spec says: bits [31:4] of the given address
   817					 * should point to the 128-bit word containing
   818					 * the desired starting pixel, and bits[3:0]
   819					 * should be between 0 and 11, indicating which
   820					 * of the 12-pixels in that 128-bit word is the
   821					 * first pixel to be used
   822					 */
   823					u32 remaining_pixels = vc4_state->src_x % 96;
   824					u32 aligned = remaining_pixels / 12;
   825					u32 last_bits = remaining_pixels % 12;
   826	
   827					x_off = aligned * 16 + last_bits;
   828					tile_w = 128;
   829					pix_per_tile = 96;
   830				} else {
   831					switch (base_format_mod) {
   832					case DRM_FORMAT_MOD_BROADCOM_SAND64:
   833						tile_w = 64;
   834						break;
   835					case DRM_FORMAT_MOD_BROADCOM_SAND128:
   836						tile_w = 128;
   837						break;
   838					case DRM_FORMAT_MOD_BROADCOM_SAND256:
   839						tile_w = 256;
   840						break;
 > 841					default:
   842						break;
   843					}
   844					pix_per_tile = tile_w / fb->format->cpp[0];
   845					x_off = (vc4_state->src_x % pix_per_tile) /
   846						(i ? h_subsample : 1) *
   847						fb->format->cpp[i];
   848				}
   849	
   850				tile = vc4_state->src_x / pix_per_tile;
   851	
   852				vc4_state->offsets[i] += param * tile_w * tile;
   853				vc4_state->offsets[i] += src_y /
   854							 (i ? v_subsample : 1) *
   855							 tile_w;
   856				vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
   857			}
   858	
   859			pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
   860			break;
   861		}
   862	
   863		default:
   864			DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
   865				      (long long)fb->modifier);
   866			return -EINVAL;
   867		}
   868	
   869		/* Don't waste cycles mixing with plane alpha if the set alpha
   870		 * is opaque or there is no per-pixel alpha information.
   871		 * In any case we use the alpha property value as the fixed alpha.
   872		 */
   873		mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
   874				  fb->format->has_alpha;
   875	
   876		if (!vc4->hvs->hvs5) {
   877		/* Control word */
   878			vc4_dlist_write(vc4_state,
   879					SCALER_CTL0_VALID |
   880					(rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
   881					(rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
   882					VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
   883					(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   884					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   885					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   886					(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
   887					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   888					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
   889	
   890			/* Position Word 0: Image Positions and Alpha Value */
   891			vc4_state->pos0_offset = vc4_state->dlist_count;
   892			vc4_dlist_write(vc4_state,
   893					VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
   894					VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
   895					VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
   896	
   897			/* Position Word 1: Scaled Image Dimensions. */
   898			if (!vc4_state->is_unity) {
   899				vc4_dlist_write(vc4_state,
   900						VC4_SET_FIELD(vc4_state->crtc_w,
   901							      SCALER_POS1_SCL_WIDTH) |
   902						VC4_SET_FIELD(vc4_state->crtc_h,
   903							      SCALER_POS1_SCL_HEIGHT));
   904			}
   905	
   906			/* Position Word 2: Source Image Size, Alpha */
   907			vc4_state->pos2_offset = vc4_state->dlist_count;
   908			vc4_dlist_write(vc4_state,
   909					VC4_SET_FIELD(fb->format->has_alpha ?
   910						      SCALER_POS2_ALPHA_MODE_PIPELINE :
   911						      SCALER_POS2_ALPHA_MODE_FIXED,
   912						      SCALER_POS2_ALPHA_MODE) |
   913					(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
   914					(fb->format->has_alpha ?
   915							SCALER_POS2_ALPHA_PREMULT : 0) |
   916					VC4_SET_FIELD(vc4_state->src_w[0],
   917						      SCALER_POS2_WIDTH) |
   918					VC4_SET_FIELD(vc4_state->src_h[0],
   919						      SCALER_POS2_HEIGHT));
   920	
   921			/* Position Word 3: Context.  Written by the HVS. */
   922			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   923	
   924		} else {
   925			u32 hvs_pixel_order = format->pixel_order;
   926	
   927			if (format->pixel_order_hvs5)
   928				hvs_pixel_order = format->pixel_order_hvs5;
   929	
   930			/* Control word */
   931			vc4_dlist_write(vc4_state,
   932					SCALER_CTL0_VALID |
   933					(hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   934					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   935					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   936					(vc4_state->is_unity ?
   937							SCALER5_CTL0_UNITY : 0) |
   938					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   939					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
   940					SCALER5_CTL0_ALPHA_EXPAND |
   941					SCALER5_CTL0_RGB_EXPAND);
   942	
   943			/* Position Word 0: Image Positions and Alpha Value */
   944			vc4_state->pos0_offset = vc4_state->dlist_count;
   945			vc4_dlist_write(vc4_state,
   946					(rotation & DRM_MODE_REFLECT_Y ?
   947							SCALER5_POS0_VFLIP : 0) |
   948					VC4_SET_FIELD(vc4_state->crtc_x,
   949						      SCALER_POS0_START_X) |
   950					(rotation & DRM_MODE_REFLECT_X ?
   951						      SCALER5_POS0_HFLIP : 0) |
   952					VC4_SET_FIELD(vc4_state->crtc_y,
   953						      SCALER5_POS0_START_Y)
   954				       );
   955	
   956			/* Control Word 2 */
   957			vc4_dlist_write(vc4_state,
   958					VC4_SET_FIELD(state->alpha >> 4,
   959						      SCALER5_CTL2_ALPHA) |
   960					(fb->format->has_alpha ?
   961						SCALER5_CTL2_ALPHA_PREMULT : 0) |
   962					(mix_plane_alpha ?
   963						SCALER5_CTL2_ALPHA_MIX : 0) |
   964					VC4_SET_FIELD(fb->format->has_alpha ?
   965					      SCALER5_CTL2_ALPHA_MODE_PIPELINE :
   966					      SCALER5_CTL2_ALPHA_MODE_FIXED,
   967					      SCALER5_CTL2_ALPHA_MODE)
   968				       );
   969	
   970			/* Position Word 1: Scaled Image Dimensions. */
   971			if (!vc4_state->is_unity) {
   972				vc4_dlist_write(vc4_state,
   973						VC4_SET_FIELD(vc4_state->crtc_w,
   974							      SCALER5_POS1_SCL_WIDTH) |
   975						VC4_SET_FIELD(vc4_state->crtc_h,
   976							      SCALER5_POS1_SCL_HEIGHT));
   977			}
   978	
   979			/* Position Word 2: Source Image Size */
   980			vc4_state->pos2_offset = vc4_state->dlist_count;
   981			vc4_dlist_write(vc4_state,
   982					VC4_SET_FIELD(vc4_state->src_w[0],
   983						      SCALER5_POS2_WIDTH) |
   984					VC4_SET_FIELD(vc4_state->src_h[0],
   985						      SCALER5_POS2_HEIGHT));
   986	
   987			/* Position Word 3: Context.  Written by the HVS. */
   988			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   989		}
   990	
   991	
   992		/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
   993		 *
   994		 * The pointers may be any byte address.
   995		 */
   996		vc4_state->ptr0_offset = vc4_state->dlist_count;
   997		for (i = 0; i < num_planes; i++)
   998			vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
   999	
  1000		/* Pointer Context Word 0/1/2: Written by the HVS */
  1001		for (i = 0; i < num_planes; i++)
  1002			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
  1003	
  1004		/* Pitch word 0 */
  1005		vc4_dlist_write(vc4_state, pitch0);
  1006	
  1007		/* Pitch word 1/2 */
  1008		for (i = 1; i < num_planes; i++) {
  1009			if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
  1010			    hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
  1011				vc4_dlist_write(vc4_state,
  1012						VC4_SET_FIELD(fb->pitches[i],
  1013							      SCALER_SRC_PITCH));
  1014			} else {
  1015				vc4_dlist_write(vc4_state, pitch0);
  1016			}
  1017		}
  1018	
  1019		/* Colorspace conversion words */
  1020		if (vc4_state->is_yuv) {
  1021			vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
  1022			vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
  1023			vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
  1024		}
  1025	
  1026		vc4_state->lbm_offset = 0;
  1027	
  1028		if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
  1029		    vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
  1030		    vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1031		    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1032			/* Reserve a slot for the LBM Base Address. The real value will
  1033			 * be set when calling vc4_plane_allocate_lbm().
  1034			 */
  1035			if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1036			    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1037				vc4_state->lbm_offset = vc4_state->dlist_count;
  1038				vc4_dlist_counter_increment(vc4_state);
  1039			}
  1040	
  1041			if (num_planes > 1) {
  1042				/* Emit Cb/Cr as channel 0 and Y as channel
  1043				 * 1. This matches how we set up scl0/scl1
  1044				 * above.
  1045				 */
  1046				vc4_write_scaling_parameters(state, 1);
  1047			}
  1048			vc4_write_scaling_parameters(state, 0);
  1049	
  1050			/* If any PPF setup was done, then all the kernel
  1051			 * pointers get uploaded.
  1052			 */
  1053			if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
  1054			    vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
  1055			    vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
  1056			    vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
  1057				u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
  1058							   SCALER_PPF_KERNEL_OFFSET);
  1059	
  1060				/* HPPF plane 0 */
  1061				vc4_dlist_write(vc4_state, kernel);
  1062				/* VPPF plane 0 */
  1063				vc4_dlist_write(vc4_state, kernel);
  1064				/* HPPF plane 1 */
  1065				vc4_dlist_write(vc4_state, kernel);
  1066				/* VPPF plane 1 */
  1067				vc4_dlist_write(vc4_state, kernel);
  1068			}
  1069		}
  1070	
  1071		vc4_state->dlist[ctl0_offset] |=
  1072			VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
  1073	
  1074		/* crtc_* are already clipped coordinates. */
  1075		covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
  1076				vc4_state->crtc_w == state->crtc->mode.hdisplay &&
  1077				vc4_state->crtc_h == state->crtc->mode.vdisplay;
  1078		/* Background fill might be necessary when the plane has per-pixel
  1079		 * alpha content or a non-opaque plane alpha and could blend from the
  1080		 * background or does not cover the entire screen.
  1081		 */
  1082		vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
  1083					   state->alpha != DRM_BLEND_ALPHA_OPAQUE;
  1084	
  1085		/* Flag the dlist as initialized to avoid checking it twice in case
  1086		 * the async update check already called vc4_plane_mode_set() and
  1087		 * decided to fallback to sync update because async update was not
  1088		 * possible.
  1089		 */
  1090		vc4_state->dlist_initialized = 1;
  1091	
  1092		vc4_plane_calc_load(state);
  1093	
  1094		return 0;
  1095	}
  1096	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [PATCH v3 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 21523 bytes --]

Hi Maxime,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.16-rc5]
[cannot apply to anholt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-randconfig-r031-20211213 (https://download.01.org/0day-ci/archive/20211214/202112141058.EBPlKMSk-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project b6a2ddb6c8ac29412b1361810972e15221fa021c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/58b0d045769ea7e075fd1968a0da080b14b9ab70
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
        git checkout 58b0d045769ea7e075fd1968a0da080b14b9ab70
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/vc4/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/vc4/vc4_plane.c:841:5: warning: variable 'tile_w' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
                                   default:
                                   ^~~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:844:20: note: uninitialized use occurs here
                                   pix_per_tile = tile_w / fb->format->cpp[0];
                                                  ^~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:812:14: note: initialize the variable 'tile_w' to silence this warning
                           u32 tile_w, tile, x_off, pix_per_tile;
                                     ^
                                      = 0
   1 warning generated.


vim +/tile_w +841 drivers/gpu/drm/vc4/vc4_plane.c

   625	
   626	/* Writes out a full display list for an active plane to the plane's
   627	 * private dlist state.
   628	 */
   629	static int vc4_plane_mode_set(struct drm_plane *plane,
   630				      struct drm_plane_state *state)
   631	{
   632		struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
   633		struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
   634		struct drm_framebuffer *fb = state->fb;
   635		u32 ctl0_offset = vc4_state->dlist_count;
   636		const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
   637		u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
   638		int num_planes = fb->format->num_planes;
   639		u32 h_subsample = fb->format->hsub;
   640		u32 v_subsample = fb->format->vsub;
   641		bool mix_plane_alpha;
   642		bool covers_screen;
   643		u32 scl0, scl1, pitch0;
   644		u32 tiling, src_y;
   645		u32 hvs_format = format->hvs;
   646		unsigned int rotation;
   647		int ret, i;
   648	
   649		if (vc4_state->dlist_initialized)
   650			return 0;
   651	
   652		ret = vc4_plane_setup_clipping_and_scaling(state);
   653		if (ret)
   654			return ret;
   655	
   656		/* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
   657		 * and 4:4:4, scl1 should be set to scl0 so both channels of
   658		 * the scaler do the same thing.  For YUV, the Y plane needs
   659		 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
   660		 * the scl fields here.
   661		 */
   662		if (num_planes == 1) {
   663			scl0 = vc4_get_scl_field(state, 0);
   664			scl1 = scl0;
   665		} else {
   666			scl0 = vc4_get_scl_field(state, 1);
   667			scl1 = vc4_get_scl_field(state, 0);
   668		}
   669	
   670		rotation = drm_rotation_simplify(state->rotation,
   671						 DRM_MODE_ROTATE_0 |
   672						 DRM_MODE_REFLECT_X |
   673						 DRM_MODE_REFLECT_Y);
   674	
   675		/* We must point to the last line when Y reflection is enabled. */
   676		src_y = vc4_state->src_y;
   677		if (rotation & DRM_MODE_REFLECT_Y)
   678			src_y += vc4_state->src_h[0] - 1;
   679	
   680		switch (base_format_mod) {
   681		case DRM_FORMAT_MOD_LINEAR:
   682			tiling = SCALER_CTL0_TILING_LINEAR;
   683			pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
   684	
   685			/* Adjust the base pointer to the first pixel to be scanned
   686			 * out.
   687			 */
   688			for (i = 0; i < num_planes; i++) {
   689				vc4_state->offsets[i] += src_y /
   690							 (i ? v_subsample : 1) *
   691							 fb->pitches[i];
   692	
   693				vc4_state->offsets[i] += vc4_state->src_x /
   694							 (i ? h_subsample : 1) *
   695							 fb->format->cpp[i];
   696			}
   697	
   698			break;
   699	
   700		case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
   701			u32 tile_size_shift = 12; /* T tiles are 4kb */
   702			/* Whole-tile offsets, mostly for setting the pitch. */
   703			u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
   704			u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
   705			u32 tile_w_mask = (1 << tile_w_shift) - 1;
   706			/* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
   707			 * the height (in pixels) of a 4k tile.
   708			 */
   709			u32 tile_h_mask = (2 << tile_h_shift) - 1;
   710			/* For T-tiled, the FB pitch is "how many bytes from one row to
   711			 * the next, such that
   712			 *
   713			 *	pitch * tile_h == tile_size * tiles_per_row
   714			 */
   715			u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
   716			u32 tiles_l = vc4_state->src_x >> tile_w_shift;
   717			u32 tiles_r = tiles_w - tiles_l;
   718			u32 tiles_t = src_y >> tile_h_shift;
   719			/* Intra-tile offsets, which modify the base address (the
   720			 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
   721			 * base address).
   722			 */
   723			u32 tile_y = (src_y >> 4) & 1;
   724			u32 subtile_y = (src_y >> 2) & 3;
   725			u32 utile_y = src_y & 3;
   726			u32 x_off = vc4_state->src_x & tile_w_mask;
   727			u32 y_off = src_y & tile_h_mask;
   728	
   729			/* When Y reflection is requested we must set the
   730			 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
   731			 * after the initial one should be fetched in descending order,
   732			 * which makes sense since we start from the last line and go
   733			 * backward.
   734			 * Don't know why we need y_off = max_y_off - y_off, but it's
   735			 * definitely required (I guess it's also related to the "going
   736			 * backward" situation).
   737			 */
   738			if (rotation & DRM_MODE_REFLECT_Y) {
   739				y_off = tile_h_mask - y_off;
   740				pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
   741			} else {
   742				pitch0 = 0;
   743			}
   744	
   745			tiling = SCALER_CTL0_TILING_256B_OR_T;
   746			pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
   747				   VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
   748				   VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
   749				   VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
   750			vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
   751			vc4_state->offsets[0] += subtile_y << 8;
   752			vc4_state->offsets[0] += utile_y << 4;
   753	
   754			/* Rows of tiles alternate left-to-right and right-to-left. */
   755			if (tiles_t & 1) {
   756				pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
   757				vc4_state->offsets[0] += (tiles_w - tiles_l) <<
   758							 tile_size_shift;
   759				vc4_state->offsets[0] -= (1 + !tile_y) << 10;
   760			} else {
   761				vc4_state->offsets[0] += tiles_l << tile_size_shift;
   762				vc4_state->offsets[0] += tile_y << 10;
   763			}
   764	
   765			break;
   766		}
   767	
   768		case DRM_FORMAT_MOD_BROADCOM_SAND64:
   769		case DRM_FORMAT_MOD_BROADCOM_SAND128:
   770		case DRM_FORMAT_MOD_BROADCOM_SAND256: {
   771			uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
   772	
   773			if (param > SCALER_TILE_HEIGHT_MASK) {
   774				DRM_DEBUG_KMS("SAND height too large (%d)\n",
   775					      param);
   776				return -EINVAL;
   777			}
   778	
   779			if (fb->format->format == DRM_FORMAT_P030) {
   780				hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
   781				tiling = SCALER_CTL0_TILING_128B;
   782			} else {
   783				hvs_format = HVS_PIXEL_FORMAT_H264;
   784	
   785				switch (base_format_mod) {
   786				case DRM_FORMAT_MOD_BROADCOM_SAND64:
   787					tiling = SCALER_CTL0_TILING_64B;
   788					break;
   789				case DRM_FORMAT_MOD_BROADCOM_SAND128:
   790					tiling = SCALER_CTL0_TILING_128B;
   791					break;
   792				case DRM_FORMAT_MOD_BROADCOM_SAND256:
   793					tiling = SCALER_CTL0_TILING_256B_OR_T;
   794					break;
   795				default:
   796					return -EINVAL;
   797					break;
   798				}
   799			}
   800	
   801			/* Adjust the base pointer to the first pixel to be scanned
   802			 * out.
   803			 *
   804			 * For P030, y_ptr [31:4] is the 128bit word for the start pixel
   805			 * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
   806			 * word that should be taken as the first pixel.
   807			 * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
   808			 * element within the 128bit word, eg for pixel 3 the value
   809			 * should be 6.
   810			 */
   811			for (i = 0; i < num_planes; i++) {
   812				u32 tile_w, tile, x_off, pix_per_tile;
   813	
   814				if (fb->format->format == DRM_FORMAT_P030) {
   815					/*
   816					 * Spec says: bits [31:4] of the given address
   817					 * should point to the 128-bit word containing
   818					 * the desired starting pixel, and bits[3:0]
   819					 * should be between 0 and 11, indicating which
   820					 * of the 12-pixels in that 128-bit word is the
   821					 * first pixel to be used
   822					 */
   823					u32 remaining_pixels = vc4_state->src_x % 96;
   824					u32 aligned = remaining_pixels / 12;
   825					u32 last_bits = remaining_pixels % 12;
   826	
   827					x_off = aligned * 16 + last_bits;
   828					tile_w = 128;
   829					pix_per_tile = 96;
   830				} else {
   831					switch (base_format_mod) {
   832					case DRM_FORMAT_MOD_BROADCOM_SAND64:
   833						tile_w = 64;
   834						break;
   835					case DRM_FORMAT_MOD_BROADCOM_SAND128:
   836						tile_w = 128;
   837						break;
   838					case DRM_FORMAT_MOD_BROADCOM_SAND256:
   839						tile_w = 256;
   840						break;
 > 841					default:
   842						break;
   843					}
   844					pix_per_tile = tile_w / fb->format->cpp[0];
   845					x_off = (vc4_state->src_x % pix_per_tile) /
   846						(i ? h_subsample : 1) *
   847						fb->format->cpp[i];
   848				}
   849	
   850				tile = vc4_state->src_x / pix_per_tile;
   851	
   852				vc4_state->offsets[i] += param * tile_w * tile;
   853				vc4_state->offsets[i] += src_y /
   854							 (i ? v_subsample : 1) *
   855							 tile_w;
   856				vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
   857			}
   858	
   859			pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
   860			break;
   861		}
   862	
   863		default:
   864			DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
   865				      (long long)fb->modifier);
   866			return -EINVAL;
   867		}
   868	
   869		/* Don't waste cycles mixing with plane alpha if the set alpha
   870		 * is opaque or there is no per-pixel alpha information.
   871		 * In any case we use the alpha property value as the fixed alpha.
   872		 */
   873		mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
   874				  fb->format->has_alpha;
   875	
   876		if (!vc4->hvs->hvs5) {
   877		/* Control word */
   878			vc4_dlist_write(vc4_state,
   879					SCALER_CTL0_VALID |
   880					(rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
   881					(rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
   882					VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
   883					(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   884					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   885					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   886					(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
   887					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   888					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
   889	
   890			/* Position Word 0: Image Positions and Alpha Value */
   891			vc4_state->pos0_offset = vc4_state->dlist_count;
   892			vc4_dlist_write(vc4_state,
   893					VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
   894					VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
   895					VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
   896	
   897			/* Position Word 1: Scaled Image Dimensions. */
   898			if (!vc4_state->is_unity) {
   899				vc4_dlist_write(vc4_state,
   900						VC4_SET_FIELD(vc4_state->crtc_w,
   901							      SCALER_POS1_SCL_WIDTH) |
   902						VC4_SET_FIELD(vc4_state->crtc_h,
   903							      SCALER_POS1_SCL_HEIGHT));
   904			}
   905	
   906			/* Position Word 2: Source Image Size, Alpha */
   907			vc4_state->pos2_offset = vc4_state->dlist_count;
   908			vc4_dlist_write(vc4_state,
   909					VC4_SET_FIELD(fb->format->has_alpha ?
   910						      SCALER_POS2_ALPHA_MODE_PIPELINE :
   911						      SCALER_POS2_ALPHA_MODE_FIXED,
   912						      SCALER_POS2_ALPHA_MODE) |
   913					(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
   914					(fb->format->has_alpha ?
   915							SCALER_POS2_ALPHA_PREMULT : 0) |
   916					VC4_SET_FIELD(vc4_state->src_w[0],
   917						      SCALER_POS2_WIDTH) |
   918					VC4_SET_FIELD(vc4_state->src_h[0],
   919						      SCALER_POS2_HEIGHT));
   920	
   921			/* Position Word 3: Context.  Written by the HVS. */
   922			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   923	
   924		} else {
   925			u32 hvs_pixel_order = format->pixel_order;
   926	
   927			if (format->pixel_order_hvs5)
   928				hvs_pixel_order = format->pixel_order_hvs5;
   929	
   930			/* Control word */
   931			vc4_dlist_write(vc4_state,
   932					SCALER_CTL0_VALID |
   933					(hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   934					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   935					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   936					(vc4_state->is_unity ?
   937							SCALER5_CTL0_UNITY : 0) |
   938					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   939					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
   940					SCALER5_CTL0_ALPHA_EXPAND |
   941					SCALER5_CTL0_RGB_EXPAND);
   942	
   943			/* Position Word 0: Image Positions and Alpha Value */
   944			vc4_state->pos0_offset = vc4_state->dlist_count;
   945			vc4_dlist_write(vc4_state,
   946					(rotation & DRM_MODE_REFLECT_Y ?
   947							SCALER5_POS0_VFLIP : 0) |
   948					VC4_SET_FIELD(vc4_state->crtc_x,
   949						      SCALER_POS0_START_X) |
   950					(rotation & DRM_MODE_REFLECT_X ?
   951						      SCALER5_POS0_HFLIP : 0) |
   952					VC4_SET_FIELD(vc4_state->crtc_y,
   953						      SCALER5_POS0_START_Y)
   954				       );
   955	
   956			/* Control Word 2 */
   957			vc4_dlist_write(vc4_state,
   958					VC4_SET_FIELD(state->alpha >> 4,
   959						      SCALER5_CTL2_ALPHA) |
   960					(fb->format->has_alpha ?
   961						SCALER5_CTL2_ALPHA_PREMULT : 0) |
   962					(mix_plane_alpha ?
   963						SCALER5_CTL2_ALPHA_MIX : 0) |
   964					VC4_SET_FIELD(fb->format->has_alpha ?
   965					      SCALER5_CTL2_ALPHA_MODE_PIPELINE :
   966					      SCALER5_CTL2_ALPHA_MODE_FIXED,
   967					      SCALER5_CTL2_ALPHA_MODE)
   968				       );
   969	
   970			/* Position Word 1: Scaled Image Dimensions. */
   971			if (!vc4_state->is_unity) {
   972				vc4_dlist_write(vc4_state,
   973						VC4_SET_FIELD(vc4_state->crtc_w,
   974							      SCALER5_POS1_SCL_WIDTH) |
   975						VC4_SET_FIELD(vc4_state->crtc_h,
   976							      SCALER5_POS1_SCL_HEIGHT));
   977			}
   978	
   979			/* Position Word 2: Source Image Size */
   980			vc4_state->pos2_offset = vc4_state->dlist_count;
   981			vc4_dlist_write(vc4_state,
   982					VC4_SET_FIELD(vc4_state->src_w[0],
   983						      SCALER5_POS2_WIDTH) |
   984					VC4_SET_FIELD(vc4_state->src_h[0],
   985						      SCALER5_POS2_HEIGHT));
   986	
   987			/* Position Word 3: Context.  Written by the HVS. */
   988			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   989		}
   990	
   991	
   992		/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
   993		 *
   994		 * The pointers may be any byte address.
   995		 */
   996		vc4_state->ptr0_offset = vc4_state->dlist_count;
   997		for (i = 0; i < num_planes; i++)
   998			vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
   999	
  1000		/* Pointer Context Word 0/1/2: Written by the HVS */
  1001		for (i = 0; i < num_planes; i++)
  1002			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
  1003	
  1004		/* Pitch word 0 */
  1005		vc4_dlist_write(vc4_state, pitch0);
  1006	
  1007		/* Pitch word 1/2 */
  1008		for (i = 1; i < num_planes; i++) {
  1009			if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
  1010			    hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
  1011				vc4_dlist_write(vc4_state,
  1012						VC4_SET_FIELD(fb->pitches[i],
  1013							      SCALER_SRC_PITCH));
  1014			} else {
  1015				vc4_dlist_write(vc4_state, pitch0);
  1016			}
  1017		}
  1018	
  1019		/* Colorspace conversion words */
  1020		if (vc4_state->is_yuv) {
  1021			vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
  1022			vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
  1023			vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
  1024		}
  1025	
  1026		vc4_state->lbm_offset = 0;
  1027	
  1028		if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
  1029		    vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
  1030		    vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1031		    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1032			/* Reserve a slot for the LBM Base Address. The real value will
  1033			 * be set when calling vc4_plane_allocate_lbm().
  1034			 */
  1035			if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1036			    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1037				vc4_state->lbm_offset = vc4_state->dlist_count;
  1038				vc4_dlist_counter_increment(vc4_state);
  1039			}
  1040	
  1041			if (num_planes > 1) {
  1042				/* Emit Cb/Cr as channel 0 and Y as channel
  1043				 * 1. This matches how we set up scl0/scl1
  1044				 * above.
  1045				 */
  1046				vc4_write_scaling_parameters(state, 1);
  1047			}
  1048			vc4_write_scaling_parameters(state, 0);
  1049	
  1050			/* If any PPF setup was done, then all the kernel
  1051			 * pointers get uploaded.
  1052			 */
  1053			if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
  1054			    vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
  1055			    vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
  1056			    vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
  1057				u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
  1058							   SCALER_PPF_KERNEL_OFFSET);
  1059	
  1060				/* HPPF plane 0 */
  1061				vc4_dlist_write(vc4_state, kernel);
  1062				/* VPPF plane 0 */
  1063				vc4_dlist_write(vc4_state, kernel);
  1064				/* HPPF plane 1 */
  1065				vc4_dlist_write(vc4_state, kernel);
  1066				/* VPPF plane 1 */
  1067				vc4_dlist_write(vc4_state, kernel);
  1068			}
  1069		}
  1070	
  1071		vc4_state->dlist[ctl0_offset] |=
  1072			VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
  1073	
  1074		/* crtc_* are already clipped coordinates. */
  1075		covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
  1076				vc4_state->crtc_w == state->crtc->mode.hdisplay &&
  1077				vc4_state->crtc_h == state->crtc->mode.vdisplay;
  1078		/* Background fill might be necessary when the plane has per-pixel
  1079		 * alpha content or a non-opaque plane alpha and could blend from the
  1080		 * background or does not cover the entire screen.
  1081		 */
  1082		vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
  1083					   state->alpha != DRM_BLEND_ALPHA_OPAQUE;
  1084	
  1085		/* Flag the dlist as initialized to avoid checking it twice in case
  1086		 * the async update check already called vc4_plane_mode_set() and
  1087		 * decided to fallback to sync update because async update was not
  1088		 * possible.
  1089		 */
  1090		vc4_state->dlist_initialized = 1;
  1091	
  1092		vc4_plane_calc_load(state);
  1093	
  1094		return 0;
  1095	}
  1096	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

Re: [PATCH v3 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030

[kernel test robot]

Hi Maxime,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.16-rc5]
[cannot apply to anholt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-randconfig-r031-20211213 (https://download.01.org/0day-ci/archive/20211214/202112141058.EBPlKMSk-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project b6a2ddb6c8ac29412b1361810972e15221fa021c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/58b0d045769ea7e075fd1968a0da080b14b9ab70
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Maxime-Ripard/drm-vc4-Support-for-30-bits-YUV-formats/20211214-005817
        git checkout 58b0d045769ea7e075fd1968a0da080b14b9ab70
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/vc4/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/vc4/vc4_plane.c:841:5: warning: variable 'tile_w' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
                                   default:
                                   ^~~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:844:20: note: uninitialized use occurs here
                                   pix_per_tile = tile_w / fb->format->cpp[0];
                                                  ^~~~~~
   drivers/gpu/drm/vc4/vc4_plane.c:812:14: note: initialize the variable 'tile_w' to silence this warning
                           u32 tile_w, tile, x_off, pix_per_tile;
                                     ^
                                      = 0
   1 warning generated.


vim +/tile_w +841 drivers/gpu/drm/vc4/vc4_plane.c

   625	
   626	/* Writes out a full display list for an active plane to the plane's
   627	 * private dlist state.
   628	 */
   629	static int vc4_plane_mode_set(struct drm_plane *plane,
   630				      struct drm_plane_state *state)
   631	{
   632		struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
   633		struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
   634		struct drm_framebuffer *fb = state->fb;
   635		u32 ctl0_offset = vc4_state->dlist_count;
   636		const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
   637		u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
   638		int num_planes = fb->format->num_planes;
   639		u32 h_subsample = fb->format->hsub;
   640		u32 v_subsample = fb->format->vsub;
   641		bool mix_plane_alpha;
   642		bool covers_screen;
   643		u32 scl0, scl1, pitch0;
   644		u32 tiling, src_y;
   645		u32 hvs_format = format->hvs;
   646		unsigned int rotation;
   647		int ret, i;
   648	
   649		if (vc4_state->dlist_initialized)
   650			return 0;
   651	
   652		ret = vc4_plane_setup_clipping_and_scaling(state);
   653		if (ret)
   654			return ret;
   655	
   656		/* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
   657		 * and 4:4:4, scl1 should be set to scl0 so both channels of
   658		 * the scaler do the same thing.  For YUV, the Y plane needs
   659		 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
   660		 * the scl fields here.
   661		 */
   662		if (num_planes == 1) {
   663			scl0 = vc4_get_scl_field(state, 0);
   664			scl1 = scl0;
   665		} else {
   666			scl0 = vc4_get_scl_field(state, 1);
   667			scl1 = vc4_get_scl_field(state, 0);
   668		}
   669	
   670		rotation = drm_rotation_simplify(state->rotation,
   671						 DRM_MODE_ROTATE_0 |
   672						 DRM_MODE_REFLECT_X |
   673						 DRM_MODE_REFLECT_Y);
   674	
   675		/* We must point to the last line when Y reflection is enabled. */
   676		src_y = vc4_state->src_y;
   677		if (rotation & DRM_MODE_REFLECT_Y)
   678			src_y += vc4_state->src_h[0] - 1;
   679	
   680		switch (base_format_mod) {
   681		case DRM_FORMAT_MOD_LINEAR:
   682			tiling = SCALER_CTL0_TILING_LINEAR;
   683			pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
   684	
   685			/* Adjust the base pointer to the first pixel to be scanned
   686			 * out.
   687			 */
   688			for (i = 0; i < num_planes; i++) {
   689				vc4_state->offsets[i] += src_y /
   690							 (i ? v_subsample : 1) *
   691							 fb->pitches[i];
   692	
   693				vc4_state->offsets[i] += vc4_state->src_x /
   694							 (i ? h_subsample : 1) *
   695							 fb->format->cpp[i];
   696			}
   697	
   698			break;
   699	
   700		case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
   701			u32 tile_size_shift = 12; /* T tiles are 4kb */
   702			/* Whole-tile offsets, mostly for setting the pitch. */
   703			u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
   704			u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
   705			u32 tile_w_mask = (1 << tile_w_shift) - 1;
   706			/* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
   707			 * the height (in pixels) of a 4k tile.
   708			 */
   709			u32 tile_h_mask = (2 << tile_h_shift) - 1;
   710			/* For T-tiled, the FB pitch is "how many bytes from one row to
   711			 * the next, such that
   712			 *
   713			 *	pitch * tile_h == tile_size * tiles_per_row
   714			 */
   715			u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
   716			u32 tiles_l = vc4_state->src_x >> tile_w_shift;
   717			u32 tiles_r = tiles_w - tiles_l;
   718			u32 tiles_t = src_y >> tile_h_shift;
   719			/* Intra-tile offsets, which modify the base address (the
   720			 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
   721			 * base address).
   722			 */
   723			u32 tile_y = (src_y >> 4) & 1;
   724			u32 subtile_y = (src_y >> 2) & 3;
   725			u32 utile_y = src_y & 3;
   726			u32 x_off = vc4_state->src_x & tile_w_mask;
   727			u32 y_off = src_y & tile_h_mask;
   728	
   729			/* When Y reflection is requested we must set the
   730			 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
   731			 * after the initial one should be fetched in descending order,
   732			 * which makes sense since we start from the last line and go
   733			 * backward.
   734			 * Don't know why we need y_off = max_y_off - y_off, but it's
   735			 * definitely required (I guess it's also related to the "going
   736			 * backward" situation).
   737			 */
   738			if (rotation & DRM_MODE_REFLECT_Y) {
   739				y_off = tile_h_mask - y_off;
   740				pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
   741			} else {
   742				pitch0 = 0;
   743			}
   744	
   745			tiling = SCALER_CTL0_TILING_256B_OR_T;
   746			pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
   747				   VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
   748				   VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
   749				   VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
   750			vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
   751			vc4_state->offsets[0] += subtile_y << 8;
   752			vc4_state->offsets[0] += utile_y << 4;
   753	
   754			/* Rows of tiles alternate left-to-right and right-to-left. */
   755			if (tiles_t & 1) {
   756				pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
   757				vc4_state->offsets[0] += (tiles_w - tiles_l) <<
   758							 tile_size_shift;
   759				vc4_state->offsets[0] -= (1 + !tile_y) << 10;
   760			} else {
   761				vc4_state->offsets[0] += tiles_l << tile_size_shift;
   762				vc4_state->offsets[0] += tile_y << 10;
   763			}
   764	
   765			break;
   766		}
   767	
   768		case DRM_FORMAT_MOD_BROADCOM_SAND64:
   769		case DRM_FORMAT_MOD_BROADCOM_SAND128:
   770		case DRM_FORMAT_MOD_BROADCOM_SAND256: {
   771			uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
   772	
   773			if (param > SCALER_TILE_HEIGHT_MASK) {
   774				DRM_DEBUG_KMS("SAND height too large (%d)\n",
   775					      param);
   776				return -EINVAL;
   777			}
   778	
   779			if (fb->format->format == DRM_FORMAT_P030) {
   780				hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
   781				tiling = SCALER_CTL0_TILING_128B;
   782			} else {
   783				hvs_format = HVS_PIXEL_FORMAT_H264;
   784	
   785				switch (base_format_mod) {
   786				case DRM_FORMAT_MOD_BROADCOM_SAND64:
   787					tiling = SCALER_CTL0_TILING_64B;
   788					break;
   789				case DRM_FORMAT_MOD_BROADCOM_SAND128:
   790					tiling = SCALER_CTL0_TILING_128B;
   791					break;
   792				case DRM_FORMAT_MOD_BROADCOM_SAND256:
   793					tiling = SCALER_CTL0_TILING_256B_OR_T;
   794					break;
   795				default:
   796					return -EINVAL;
   797					break;
   798				}
   799			}
   800	
   801			/* Adjust the base pointer to the first pixel to be scanned
   802			 * out.
   803			 *
   804			 * For P030, y_ptr [31:4] is the 128bit word for the start pixel
   805			 * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
   806			 * word that should be taken as the first pixel.
   807			 * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
   808			 * element within the 128bit word, eg for pixel 3 the value
   809			 * should be 6.
   810			 */
   811			for (i = 0; i < num_planes; i++) {
   812				u32 tile_w, tile, x_off, pix_per_tile;
   813	
   814				if (fb->format->format == DRM_FORMAT_P030) {
   815					/*
   816					 * Spec says: bits [31:4] of the given address
   817					 * should point to the 128-bit word containing
   818					 * the desired starting pixel, and bits[3:0]
   819					 * should be between 0 and 11, indicating which
   820					 * of the 12-pixels in that 128-bit word is the
   821					 * first pixel to be used
   822					 */
   823					u32 remaining_pixels = vc4_state->src_x % 96;
   824					u32 aligned = remaining_pixels / 12;
   825					u32 last_bits = remaining_pixels % 12;
   826	
   827					x_off = aligned * 16 + last_bits;
   828					tile_w = 128;
   829					pix_per_tile = 96;
   830				} else {
   831					switch (base_format_mod) {
   832					case DRM_FORMAT_MOD_BROADCOM_SAND64:
   833						tile_w = 64;
   834						break;
   835					case DRM_FORMAT_MOD_BROADCOM_SAND128:
   836						tile_w = 128;
   837						break;
   838					case DRM_FORMAT_MOD_BROADCOM_SAND256:
   839						tile_w = 256;
   840						break;
 > 841					default:
   842						break;
   843					}
   844					pix_per_tile = tile_w / fb->format->cpp[0];
   845					x_off = (vc4_state->src_x % pix_per_tile) /
   846						(i ? h_subsample : 1) *
   847						fb->format->cpp[i];
   848				}
   849	
   850				tile = vc4_state->src_x / pix_per_tile;
   851	
   852				vc4_state->offsets[i] += param * tile_w * tile;
   853				vc4_state->offsets[i] += src_y /
   854							 (i ? v_subsample : 1) *
   855							 tile_w;
   856				vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
   857			}
   858	
   859			pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
   860			break;
   861		}
   862	
   863		default:
   864			DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
   865				      (long long)fb->modifier);
   866			return -EINVAL;
   867		}
   868	
   869		/* Don't waste cycles mixing with plane alpha if the set alpha
   870		 * is opaque or there is no per-pixel alpha information.
   871		 * In any case we use the alpha property value as the fixed alpha.
   872		 */
   873		mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
   874				  fb->format->has_alpha;
   875	
   876		if (!vc4->hvs->hvs5) {
   877		/* Control word */
   878			vc4_dlist_write(vc4_state,
   879					SCALER_CTL0_VALID |
   880					(rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
   881					(rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
   882					VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
   883					(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   884					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   885					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   886					(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
   887					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   888					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
   889	
   890			/* Position Word 0: Image Positions and Alpha Value */
   891			vc4_state->pos0_offset = vc4_state->dlist_count;
   892			vc4_dlist_write(vc4_state,
   893					VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
   894					VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
   895					VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
   896	
   897			/* Position Word 1: Scaled Image Dimensions. */
   898			if (!vc4_state->is_unity) {
   899				vc4_dlist_write(vc4_state,
   900						VC4_SET_FIELD(vc4_state->crtc_w,
   901							      SCALER_POS1_SCL_WIDTH) |
   902						VC4_SET_FIELD(vc4_state->crtc_h,
   903							      SCALER_POS1_SCL_HEIGHT));
   904			}
   905	
   906			/* Position Word 2: Source Image Size, Alpha */
   907			vc4_state->pos2_offset = vc4_state->dlist_count;
   908			vc4_dlist_write(vc4_state,
   909					VC4_SET_FIELD(fb->format->has_alpha ?
   910						      SCALER_POS2_ALPHA_MODE_PIPELINE :
   911						      SCALER_POS2_ALPHA_MODE_FIXED,
   912						      SCALER_POS2_ALPHA_MODE) |
   913					(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
   914					(fb->format->has_alpha ?
   915							SCALER_POS2_ALPHA_PREMULT : 0) |
   916					VC4_SET_FIELD(vc4_state->src_w[0],
   917						      SCALER_POS2_WIDTH) |
   918					VC4_SET_FIELD(vc4_state->src_h[0],
   919						      SCALER_POS2_HEIGHT));
   920	
   921			/* Position Word 3: Context.  Written by the HVS. */
   922			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   923	
   924		} else {
   925			u32 hvs_pixel_order = format->pixel_order;
   926	
   927			if (format->pixel_order_hvs5)
   928				hvs_pixel_order = format->pixel_order_hvs5;
   929	
   930			/* Control word */
   931			vc4_dlist_write(vc4_state,
   932					SCALER_CTL0_VALID |
   933					(hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
   934					(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
   935					VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
   936					(vc4_state->is_unity ?
   937							SCALER5_CTL0_UNITY : 0) |
   938					VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
   939					VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
   940					SCALER5_CTL0_ALPHA_EXPAND |
   941					SCALER5_CTL0_RGB_EXPAND);
   942	
   943			/* Position Word 0: Image Positions and Alpha Value */
   944			vc4_state->pos0_offset = vc4_state->dlist_count;
   945			vc4_dlist_write(vc4_state,
   946					(rotation & DRM_MODE_REFLECT_Y ?
   947							SCALER5_POS0_VFLIP : 0) |
   948					VC4_SET_FIELD(vc4_state->crtc_x,
   949						      SCALER_POS0_START_X) |
   950					(rotation & DRM_MODE_REFLECT_X ?
   951						      SCALER5_POS0_HFLIP : 0) |
   952					VC4_SET_FIELD(vc4_state->crtc_y,
   953						      SCALER5_POS0_START_Y)
   954				       );
   955	
   956			/* Control Word 2 */
   957			vc4_dlist_write(vc4_state,
   958					VC4_SET_FIELD(state->alpha >> 4,
   959						      SCALER5_CTL2_ALPHA) |
   960					(fb->format->has_alpha ?
   961						SCALER5_CTL2_ALPHA_PREMULT : 0) |
   962					(mix_plane_alpha ?
   963						SCALER5_CTL2_ALPHA_MIX : 0) |
   964					VC4_SET_FIELD(fb->format->has_alpha ?
   965					      SCALER5_CTL2_ALPHA_MODE_PIPELINE :
   966					      SCALER5_CTL2_ALPHA_MODE_FIXED,
   967					      SCALER5_CTL2_ALPHA_MODE)
   968				       );
   969	
   970			/* Position Word 1: Scaled Image Dimensions. */
   971			if (!vc4_state->is_unity) {
   972				vc4_dlist_write(vc4_state,
   973						VC4_SET_FIELD(vc4_state->crtc_w,
   974							      SCALER5_POS1_SCL_WIDTH) |
   975						VC4_SET_FIELD(vc4_state->crtc_h,
   976							      SCALER5_POS1_SCL_HEIGHT));
   977			}
   978	
   979			/* Position Word 2: Source Image Size */
   980			vc4_state->pos2_offset = vc4_state->dlist_count;
   981			vc4_dlist_write(vc4_state,
   982					VC4_SET_FIELD(vc4_state->src_w[0],
   983						      SCALER5_POS2_WIDTH) |
   984					VC4_SET_FIELD(vc4_state->src_h[0],
   985						      SCALER5_POS2_HEIGHT));
   986	
   987			/* Position Word 3: Context.  Written by the HVS. */
   988			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
   989		}
   990	
   991	
   992		/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
   993		 *
   994		 * The pointers may be any byte address.
   995		 */
   996		vc4_state->ptr0_offset = vc4_state->dlist_count;
   997		for (i = 0; i < num_planes; i++)
   998			vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
   999	
  1000		/* Pointer Context Word 0/1/2: Written by the HVS */
  1001		for (i = 0; i < num_planes; i++)
  1002			vc4_dlist_write(vc4_state, 0xc0c0c0c0);
  1003	
  1004		/* Pitch word 0 */
  1005		vc4_dlist_write(vc4_state, pitch0);
  1006	
  1007		/* Pitch word 1/2 */
  1008		for (i = 1; i < num_planes; i++) {
  1009			if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
  1010			    hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
  1011				vc4_dlist_write(vc4_state,
  1012						VC4_SET_FIELD(fb->pitches[i],
  1013							      SCALER_SRC_PITCH));
  1014			} else {
  1015				vc4_dlist_write(vc4_state, pitch0);
  1016			}
  1017		}
  1018	
  1019		/* Colorspace conversion words */
  1020		if (vc4_state->is_yuv) {
  1021			vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
  1022			vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
  1023			vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
  1024		}
  1025	
  1026		vc4_state->lbm_offset = 0;
  1027	
  1028		if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
  1029		    vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
  1030		    vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1031		    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1032			/* Reserve a slot for the LBM Base Address. The real value will
  1033			 * be set when calling vc4_plane_allocate_lbm().
  1034			 */
  1035			if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
  1036			    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
  1037				vc4_state->lbm_offset = vc4_state->dlist_count;
  1038				vc4_dlist_counter_increment(vc4_state);
  1039			}
  1040	
  1041			if (num_planes > 1) {
  1042				/* Emit Cb/Cr as channel 0 and Y as channel
  1043				 * 1. This matches how we set up scl0/scl1
  1044				 * above.
  1045				 */
  1046				vc4_write_scaling_parameters(state, 1);
  1047			}
  1048			vc4_write_scaling_parameters(state, 0);
  1049	
  1050			/* If any PPF setup was done, then all the kernel
  1051			 * pointers get uploaded.
  1052			 */
  1053			if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
  1054			    vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
  1055			    vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
  1056			    vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
  1057				u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
  1058							   SCALER_PPF_KERNEL_OFFSET);
  1059	
  1060				/* HPPF plane 0 */
  1061				vc4_dlist_write(vc4_state, kernel);
  1062				/* VPPF plane 0 */
  1063				vc4_dlist_write(vc4_state, kernel);
  1064				/* HPPF plane 1 */
  1065				vc4_dlist_write(vc4_state, kernel);
  1066				/* VPPF plane 1 */
  1067				vc4_dlist_write(vc4_state, kernel);
  1068			}
  1069		}
  1070	
  1071		vc4_state->dlist[ctl0_offset] |=
  1072			VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
  1073	
  1074		/* crtc_* are already clipped coordinates. */
  1075		covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
  1076				vc4_state->crtc_w == state->crtc->mode.hdisplay &&
  1077				vc4_state->crtc_h == state->crtc->mode.vdisplay;
  1078		/* Background fill might be necessary when the plane has per-pixel
  1079		 * alpha content or a non-opaque plane alpha and could blend from the
  1080		 * background or does not cover the entire screen.
  1081		 */
  1082		vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
  1083					   state->alpha != DRM_BLEND_ALPHA_OPAQUE;
  1084	
  1085		/* Flag the dlist as initialized to avoid checking it twice in case
  1086		 * the async update check already called vc4_plane_mode_set() and
  1087		 * decided to fallback to sync update because async update was not
  1088		 * possible.
  1089		 */
  1090		vc4_state->dlist_initialized = 1;
  1091	
  1092		vc4_plane_calc_load(state);
  1093	
  1094		return 0;
  1095	}
  1096	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[PATCH v3 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges

[Maxime Ripard]

From: Dave Stevenson <dave.stevenson@raspberrypi.com>

The BT601/BT709 color encoding and limited vs full
range properties were not being exposed, defaulting
always to BT601 limited range.

Expose the parameters and set the registers appropriately.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_plane.c | 71 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/vc4/vc4_regs.h  | 19 ++++++---
 2 files changed, 82 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 18627b240a55..1155b0beb620 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -623,6 +623,51 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
 	return 0;
 }
 
+/*
+ * The colorspace conversion matrices are held in 3 entries in the dlist.
+ * Create an array of them, with entries for each full and limited mode, and
+ * each supported colorspace.
+ */
+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
+	{
+		/* Limited range */
+		{
+			/* BT601 */
+			SCALER_CSC0_ITR_R_601_5,
+			SCALER_CSC1_ITR_R_601_5,
+			SCALER_CSC2_ITR_R_601_5,
+		}, {
+			/* BT709 */
+			SCALER_CSC0_ITR_R_709_3,
+			SCALER_CSC1_ITR_R_709_3,
+			SCALER_CSC2_ITR_R_709_3,
+		}, {
+			/* BT2020 */
+			SCALER_CSC0_ITR_R_2020,
+			SCALER_CSC1_ITR_R_2020,
+			SCALER_CSC2_ITR_R_2020,
+		}
+	}, {
+		/* Full range */
+		{
+			/* JFIF */
+			SCALER_CSC0_JPEG_JFIF,
+			SCALER_CSC1_JPEG_JFIF,
+			SCALER_CSC2_JPEG_JFIF,
+		}, {
+			/* BT709 */
+			SCALER_CSC0_ITR_R_709_3_FR,
+			SCALER_CSC1_ITR_R_709_3_FR,
+			SCALER_CSC2_ITR_R_709_3_FR,
+		}, {
+			/* BT2020 */
+			SCALER_CSC0_ITR_R_2020_FR,
+			SCALER_CSC1_ITR_R_2020_FR,
+			SCALER_CSC2_ITR_R_2020_FR,
+		}
+	}
+};
+
 /* Writes out a full display list for an active plane to the plane's
  * private dlist state.
  */
@@ -1018,9 +1063,20 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
 
 	/* Colorspace conversion words */
 	if (vc4_state->is_yuv) {
-		vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
-		vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
-		vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
+		enum drm_color_encoding color_encoding = state->color_encoding;
+		enum drm_color_range color_range = state->color_range;
+		const u32 *ccm;
+
+		if (color_encoding >= DRM_COLOR_ENCODING_MAX)
+			color_encoding = DRM_COLOR_YCBCR_BT601;
+		if (color_range >= DRM_COLOR_RANGE_MAX)
+			color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
+
+		ccm = colorspace_coeffs[color_range][color_encoding];
+
+		vc4_dlist_write(vc4_state, ccm[0]);
+		vc4_dlist_write(vc4_state, ccm[1]);
+		vc4_dlist_write(vc4_state, ccm[2]);
 	}
 
 	vc4_state->lbm_offset = 0;
@@ -1449,6 +1505,15 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 					   DRM_MODE_REFLECT_X |
 					   DRM_MODE_REFLECT_Y);
 
+	drm_plane_create_color_properties(plane,
+					  BIT(DRM_COLOR_YCBCR_BT601) |
+					  BIT(DRM_COLOR_YCBCR_BT709) |
+					  BIT(DRM_COLOR_YCBCR_BT2020),
+					  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+					  BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+					  DRM_COLOR_YCBCR_BT709,
+					  DRM_COLOR_YCBCR_LIMITED_RANGE);
+
 	return plane;
 }
 
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 489f921ef44d..7538b84a6dca 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -975,7 +975,10 @@ enum hvs_pixel_format {
 #define SCALER_CSC0_COEF_CR_OFS_SHIFT		0
 #define SCALER_CSC0_ITR_R_601_5			0x00f00000
 #define SCALER_CSC0_ITR_R_709_3			0x00f00000
+#define SCALER_CSC0_ITR_R_2020			0x00f00000
 #define SCALER_CSC0_JPEG_JFIF			0x00000000
+#define SCALER_CSC0_ITR_R_709_3_FR		0x00000000
+#define SCALER_CSC0_ITR_R_2020_FR		0x00000000
 
 /* S2.8 contribution of Cb to Green */
 #define SCALER_CSC1_COEF_CB_GRN_MASK		VC4_MASK(31, 22)
@@ -990,8 +993,11 @@ enum hvs_pixel_format {
 #define SCALER_CSC1_COEF_CR_BLU_MASK		VC4_MASK(1, 0)
 #define SCALER_CSC1_COEF_CR_BLU_SHIFT		0
 #define SCALER_CSC1_ITR_R_601_5			0xe73304a8
-#define SCALER_CSC1_ITR_R_709_3			0xf2b784a8
-#define SCALER_CSC1_JPEG_JFIF			0xea34a400
+#define SCALER_CSC1_ITR_R_709_3			0xf27784a8
+#define SCALER_CSC1_ITR_R_2020			0xf43594a8
+#define SCALER_CSC1_JPEG_JFIF			0xea349400
+#define SCALER_CSC1_ITR_R_709_3_FR		0xf4388400
+#define SCALER_CSC1_ITR_R_2020_FR		0xf5b6d400
 
 /* S2.8 contribution of Cb to Red */
 #define SCALER_CSC2_COEF_CB_RED_MASK		VC4_MASK(29, 20)
@@ -1002,9 +1008,12 @@ enum hvs_pixel_format {
 /* S2.8 contribution of Cb to Blue */
 #define SCALER_CSC2_COEF_CB_BLU_MASK		VC4_MASK(19, 10)
 #define SCALER_CSC2_COEF_CB_BLU_SHIFT		10
-#define SCALER_CSC2_ITR_R_601_5			0x00066204
-#define SCALER_CSC2_ITR_R_709_3			0x00072a1c
-#define SCALER_CSC2_JPEG_JFIF			0x000599c5
+#define SCALER_CSC2_ITR_R_601_5			0x00066604
+#define SCALER_CSC2_ITR_R_709_3			0x00072e1d
+#define SCALER_CSC2_ITR_R_2020			0x0006b624
+#define SCALER_CSC2_JPEG_JFIF			0x00059dc6
+#define SCALER_CSC2_ITR_R_709_3_FR		0x00064ddb
+#define SCALER_CSC2_ITR_R_2020_FR		0x0005e5e2
 
 #define SCALER_TPZ0_VERT_RECALC			BIT(31)
 #define SCALER_TPZ0_SCALE_MASK			VC4_MASK(28, 8)
-- 
2.33.1