[agd5f:drm-next-5.17 85/342] drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:64:18: warning: variable 'ecc_err_cnt' set but not used

[kernel test robot <lkp@intel.com>]

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Hi Stanley.Yang,

FYI, the error/warning still remains.

tree:   https://gitlab.freedesktop.org/agd5f/linux.git drm-next-5.17
head:   46dbcbf47e6871e142ada8a8188b7a4fc8f1d808
commit: 8882f90a3fe2457c8b3f86bbbbef8754f704f5ef [85/342] drm/amdgpu: add new query interface for umc block v2
config: alpha-randconfig-r004-20211122 (https://download.01.org/0day-ci/archive/20211230/202112301449.EEf5bQCC-lkp(a)intel.com/config)
compiler: alpha-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git remote add agd5f https://gitlab.freedesktop.org/agd5f/linux.git
        git fetch --no-tags agd5f drm-next-5.17
        git checkout 8882f90a3fe2457c8b3f86bbbbef8754f704f5ef
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=alpha SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/ drivers/gpu/drm/amd/pm/swsmu/smu11/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/umc_v6_7.c: In function 'umc_v6_7_ecc_info_query_correctable_error_count':
>> drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:64:18: warning: variable 'ecc_err_cnt' set but not used [-Wunused-but-set-variable]
      64 |         uint32_t ecc_err_cnt;
         |                  ^~~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/umc_v6_7.c: In function 'umc_v6_7_ecc_info_query_ras_error_count':
>> drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:113:18: warning: variable 'umc_reg_offset' set but not used [-Wunused-but-set-variable]
     113 |         uint32_t umc_reg_offset  = 0;
         |                  ^~~~~~~~~~~~~~


vim +/ecc_err_cnt +64 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

    59	
    60	static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
    61							   uint32_t channel_index,
    62							   unsigned long *error_count)
    63	{
  > 64		uint32_t ecc_err_cnt;
    65		uint64_t mc_umc_status;
    66		struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
    67	
    68		/*
    69		 * select the lower chip and check the error count
    70		 * skip add error count, calc error counter only from mca_umc_status
    71		 */
    72		ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_lo_chip;
    73	
    74		/*
    75		 * select the higher chip and check the err counter
    76		 * skip add error count, calc error counter only from mca_umc_status
    77		 */
    78		ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_hi_chip;
    79	
    80		/* check for SRAM correctable error
    81		  MCUMC_STATUS is a 64 bit register */
    82		mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
    83		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
    84		    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
    85			*error_count += 1;
    86	}
    87	
    88	static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev,
    89							      uint32_t channel_index,
    90							      unsigned long *error_count)
    91	{
    92		uint64_t mc_umc_status;
    93		struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
    94	
    95		/* check the MCUMC_STATUS */
    96		mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
    97		if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
    98		    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
    99		    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
   100		    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
   101		    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
   102		    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
   103			*error_count += 1;
   104	}
   105	
   106	static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
   107						   void *ras_error_status)
   108	{
   109		struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
   110	
   111		uint32_t umc_inst        = 0;
   112		uint32_t ch_inst         = 0;
 > 113		uint32_t umc_reg_offset  = 0;
   114		uint32_t channel_index	 = 0;
   115	
   116		/*TODO: driver needs to toggle DF Cstate to ensure
   117		 * safe access of UMC registers. Will add the protection */
   118		LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
   119			umc_reg_offset = get_umc_v6_7_reg_offset(adev,
   120								 umc_inst,
   121								 ch_inst);
   122			channel_index = get_umc_v6_7_channel_index(adev,
   123								 umc_inst,
   124								 ch_inst);
   125			umc_v6_7_ecc_info_query_correctable_error_count(adev,
   126							      channel_index,
   127							      &(err_data->ce_count));
   128			umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev,
   129								  channel_index,
   130								  &(err_data->ue_count));
   131		}
   132	}
   133	

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