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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Rob Herring <robh+dt@kernel.org>
Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: Re: [PATCH v5 3/4] clk: visconti: Add support common clock driver and reset driver
Date: Wed, 05 Jan 2022 17:14:30 -0800	[thread overview]
Message-ID: <20220106011431.4BACAC36AEB@smtp.kernel.org> (raw)
In-Reply-To: <20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp>

Quoting Nobuhiro Iwamatsu (2021-10-24 20:10:37)
> Add support for common interface of the common clock and reset driver
> for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL,
> and the PISMU provides clock and reset functionality.
> Each drivers are provided in this patch.
> 
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
> ---

Applied to clk-next

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Rob Herring <robh+dt@kernel.org>
Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: Re: [PATCH v5 3/4] clk: visconti: Add support common clock driver and reset driver
Date: Wed, 05 Jan 2022 17:14:30 -0800	[thread overview]
Message-ID: <20220106011431.4BACAC36AEB@smtp.kernel.org> (raw)
In-Reply-To: <20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp>

Quoting Nobuhiro Iwamatsu (2021-10-24 20:10:37)
> Add support for common interface of the common clock and reset driver
> for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL,
> and the PISMU provides clock and reset functionality.
> Each drivers are provided in this patch.
> 
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
> ---

Applied to clk-next

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  parent reply	other threads:[~2022-01-06  1:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25  3:10 [PATCH v5 0/4] clk: visconti: Add support common clock driver and reset driver Nobuhiro Iwamatsu
2021-10-25  3:10 ` Nobuhiro Iwamatsu
2021-10-25  3:10 ` [PATCH v5 1/4] dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC Nobuhiro Iwamatsu
2021-10-25  3:10   ` Nobuhiro Iwamatsu
2022-01-06  1:14   ` Stephen Boyd
2022-01-06  1:14     ` Stephen Boyd
2021-10-25  3:10 ` [PATCH v5 2/4] dt-bindings: clock: Add DT bindings for SMU " Nobuhiro Iwamatsu
2021-10-25  3:10   ` Nobuhiro Iwamatsu
2022-01-06  1:14   ` Stephen Boyd
2022-01-06  1:14     ` Stephen Boyd
2021-10-25  3:10 ` [PATCH v5 3/4] clk: visconti: Add support common clock driver and reset driver Nobuhiro Iwamatsu
2021-10-25  3:10   ` Nobuhiro Iwamatsu
2021-10-26  5:38   ` kernel test robot
2021-10-27  8:40   ` kernel test robot
2021-10-27  8:40     ` kernel test robot
2022-01-06  1:14   ` Stephen Boyd [this message]
2022-01-06  1:14     ` Stephen Boyd
2021-10-25  3:10 ` [PATCH v5 4/4] MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller Nobuhiro Iwamatsu
2021-10-25  3:10   ` Nobuhiro Iwamatsu
2022-01-06  1:14   ` Stephen Boyd
2022-01-06  1:14     ` Stephen Boyd

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