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* [Buildroot] [PATCH 1/2] package/riscv-isa-sim: new package
@ 2022-01-09 16:47 Julien Olivain
  2022-01-09 16:47 ` [Buildroot] [PATCH 2/2] configs/spike_riscv64: new defconfig Julien Olivain
  2022-01-11 22:08 ` [Buildroot] [PATCH 1/2] package/riscv-isa-sim: new package Thomas Petazzoni
  0 siblings, 2 replies; 4+ messages in thread
From: Julien Olivain @ 2022-01-09 16:47 UTC (permalink / raw)
  To: buildroot; +Cc: Julien Olivain, Thomas Petazzoni

Spike, the RISC-V ISA Simulator, implements a functional model of one
or more RISC-V harts.

The host package provides an alternative solution to qemu.

https://github.com/riscv-software-src/riscv-isa-sim

Signed-off-by: Julien Olivain <ju.o@free.fr>
---
 DEVELOPERS                                    |  1 +
 package/Config.in                             |  1 +
 package/Config.in.host                        |  1 +
 ...01-riscv-disable-precompiled-headers.patch | 34 +++++++++++++++++++
 package/riscv-isa-sim/Config.in               | 18 ++++++++++
 package/riscv-isa-sim/Config.in.host          | 13 +++++++
 package/riscv-isa-sim/riscv-isa-sim.hash      |  3 ++
 package/riscv-isa-sim/riscv-isa-sim.mk        | 13 +++++++
 8 files changed, 84 insertions(+)
 create mode 100644 package/riscv-isa-sim/0001-riscv-disable-precompiled-headers.patch
 create mode 100644 package/riscv-isa-sim/Config.in
 create mode 100644 package/riscv-isa-sim/Config.in.host
 create mode 100644 package/riscv-isa-sim/riscv-isa-sim.hash
 create mode 100644 package/riscv-isa-sim/riscv-isa-sim.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index ed65c74319..59a8dba2ab 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1588,6 +1588,7 @@ F:	package/fluidsynth/
 F:	package/glslsandbox-player/
 F:	package/ptm2human/
 F:	package/python-pyalsa/
+F:	package/riscv-isa-sim/
 
 N:	Julien Viard de Galbert <julien@vdg.name>
 F:	package/dieharder/
diff --git a/package/Config.in b/package/Config.in
index 85193f7802..b20cf45698 100644
--- a/package/Config.in
+++ b/package/Config.in
@@ -2126,6 +2126,7 @@ menu "Miscellaneous"
 	source "package/proj/Config.in"
 	source "package/qemu/Config.in"
 	source "package/qpdf/Config.in"
+	source "package/riscv-isa-sim/Config.in"
 	source "package/rtl_433/Config.in"
 	source "package/shared-mime-info/Config.in"
 	source "package/sunwait/Config.in"
diff --git a/package/Config.in.host b/package/Config.in.host
index b3e00bb482..22aafb858a 100644
--- a/package/Config.in.host
+++ b/package/Config.in.host
@@ -77,6 +77,7 @@ menu "Host utilities"
 	source "package/qoriq-rcw/Config.in.host"
 	source "package/raspberrypi-usbboot/Config.in.host"
 	source "package/rauc/Config.in.host"
+	source "package/riscv-isa-sim/Config.in.host"
 	source "package/rustc/Config.in.host"
 	source "package/s6-rc/Config.in.host"
 	source "package/sam-ba/Config.in.host"
diff --git a/package/riscv-isa-sim/0001-riscv-disable-precompiled-headers.patch b/package/riscv-isa-sim/0001-riscv-disable-precompiled-headers.patch
new file mode 100644
index 0000000000..461f34e3a1
--- /dev/null
+++ b/package/riscv-isa-sim/0001-riscv-disable-precompiled-headers.patch
@@ -0,0 +1,34 @@
+From 980d5143089bf32ef8a6dfdf1bb9e9fe92fa7bf5 Mon Sep 17 00:00:00 2001
+From: Julien Olivain <ju.o@free.fr>
+Date: Sun, 9 Jan 2022 13:38:48 +0100
+Subject: [PATCH] riscv: disable precompiled headers
+
+While precompiling header, some toolchains fail with the message:
+
+    /path/to/toolchain/bin/ld: /path/to/sysroot/usr/lib/Scrt1.o: in function `_start':
+    (.text+0x54): undefined reference to `main'
+
+The patch totally disable precompiled headers.
+
+Signed-off-by: Julien Olivain <ju.o@free.fr>
+---
+ riscv/riscv.mk.in | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
+index 2347ce6..4f56eaf 100644
+--- a/riscv/riscv.mk.in
++++ b/riscv/riscv.mk.in
+@@ -35,9 +35,6 @@ riscv_hdrs = \
+ 
+ riscv_install_hdrs = mmio_plugin.h
+ 
+-riscv_precompiled_hdrs = \
+-	insn_template.h \
+-
+ riscv_srcs = \
+ 	processor.cc \
+ 	execute.cc \
+-- 
+2.34.1
+
diff --git a/package/riscv-isa-sim/Config.in b/package/riscv-isa-sim/Config.in
new file mode 100644
index 0000000000..1f5c8aad18
--- /dev/null
+++ b/package/riscv-isa-sim/Config.in
@@ -0,0 +1,18 @@
+config BR2_PACKAGE_RISCV_ISA_SIM
+	bool "riscv-isa-sim"
+	depends on BR2_INSTALL_LIBSTDCPP
+	depends on BR2_TOOLCHAIN_GCC_AT_LEAST_4_9 # C++11
+	depends on BR2_TOOLCHAIN_HAS_THREADS
+	depends on !BR2_STATIC_LIBS
+	help
+	  Spike, the RISC-V ISA Simulator, implements a functional
+	  model of one or more RISC-V harts.
+
+	  https://github.com/riscv-software-src/riscv-isa-sim
+
+comment "riscv-isa-sim needs a toolchain w/ C++11, threads, wchar and dynamic library"
+	depends on !BR2_INSTALL_LIBSTDCPP || \
+		!BR2_TOOLCHAIN_GCC_AT_LEAST_4_9 || \
+		!BR2_TOOLCHAIN_HAS_THREADS || \
+		!BR2_USE_WCHAR || \
+		BR2_STATIC
diff --git a/package/riscv-isa-sim/Config.in.host b/package/riscv-isa-sim/Config.in.host
new file mode 100644
index 0000000000..01a189a075
--- /dev/null
+++ b/package/riscv-isa-sim/Config.in.host
@@ -0,0 +1,13 @@
+config BR2_PACKAGE_HOST_RISCV_ISA_SIM
+	bool "host riscv-isa-sim"
+	depends on BR2_TOOLCHAIN_GCC_AT_LEAST_4_9 # C++11
+	help
+	  Spike, the RISC-V ISA Simulator, implements a functional
+	  model of one or more RISC-V harts.
+
+	  The host package provides an alternative solution to qemu.
+
+	  https://github.com/riscv-software-src/riscv-isa-sim
+
+comment "host riscv-isa-sim needs a toolchain w/ C++11"
+	depends on !BR2_TOOLCHAIN_GCC_AT_LEAST_4_9
diff --git a/package/riscv-isa-sim/riscv-isa-sim.hash b/package/riscv-isa-sim/riscv-isa-sim.hash
new file mode 100644
index 0000000000..d787a03e4c
--- /dev/null
+++ b/package/riscv-isa-sim/riscv-isa-sim.hash
@@ -0,0 +1,3 @@
+# Locally computed
+sha256  9b29c220fed1e867e3bea4b5c565f2629237d525a4d9fe1668699c4406003a1f  riscv-isa-sim-1.1.0.tar.gz
+sha256  c65e436d18972c9c4bd192494fe4870bd2e158179474975b80a3559f27631632  LICENSE
diff --git a/package/riscv-isa-sim/riscv-isa-sim.mk b/package/riscv-isa-sim/riscv-isa-sim.mk
new file mode 100644
index 0000000000..df5d4db9a2
--- /dev/null
+++ b/package/riscv-isa-sim/riscv-isa-sim.mk
@@ -0,0 +1,13 @@
+################################################################################
+#
+# riscv-isa-sim
+#
+################################################################################
+
+RISCV_ISA_SIM_VERSION = 1.1.0
+RISCV_ISA_SIM_SITE = $(call github,riscv-software-src,riscv-isa-sim,v$(RISCV_ISA_SIM_VERSION))
+RISCV_ISA_SIM_LICENSE = BSD-3-Clause
+RISCV_ISA_SIM_LICENSE_FILES = LICENSE
+
+$(eval $(autotools-package))
+$(eval $(host-autotools-package))
-- 
2.34.1

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Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-09 16:47 [Buildroot] [PATCH 1/2] package/riscv-isa-sim: new package Julien Olivain
2022-01-09 16:47 ` [Buildroot] [PATCH 2/2] configs/spike_riscv64: new defconfig Julien Olivain
2022-01-11 22:08   ` Thomas Petazzoni
2022-01-11 22:08 ` [Buildroot] [PATCH 1/2] package/riscv-isa-sim: new package Thomas Petazzoni

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