* [Buildroot] [PATCH 01/16] toolchain/toolchain-external/toolchain-external-bootlin: re-update OpenRISC toolchains
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
@ 2022-01-24 23:00 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 02/16] support/scripts/gen-bootlin-toolchains: add support for new x86-64 toolchains Thomas Petazzoni
` (15 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:00 UTC (permalink / raw)
To: Buildroot List
Cc: Thomas De Schampheleire, Romain Naour, Giulio Benetti,
Yann E. MORIN, Thomas Petazzoni
The OpenRISC toolchains have been rebuilt once again, this time with
the _REENTRANT fixed merged in commit
98e39dc80ee81a166df90b4ff3232038a63b759c ("package/gcc: define
_REENTRANT for OpenRISC when -pthread is passed")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
.../toolchain-external-bootlin/Config.in.options | 8 ++++----
.../toolchain-external-bootlin.hash | 16 ++++++++--------
.../toolchain-external-bootlin.mk | 8 ++++----
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
index 94dea4a386..55b6d4c786 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
@@ -2400,7 +2400,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_NIOS2_GLIBC_STABLE
https://toolchains.bootlin.com/
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_BLEEDING_EDGE
- bool "openrisc musl bleeding-edge 2021.11-4"
+ bool "openrisc musl bleeding-edge 2021.11-5"
depends on BR2_or1k
depends on BR2_USE_MMU
select BR2_TOOLCHAIN_GCC_AT_LEAST_11
@@ -2423,7 +2423,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_BLEEDING_EDGE
https://toolchains.bootlin.com/
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_STABLE
- bool "openrisc musl stable 2021.11-4"
+ bool "openrisc musl stable 2021.11-5"
depends on BR2_or1k
depends on BR2_USE_MMU
select BR2_TOOLCHAIN_GCC_AT_LEAST_10
@@ -2445,7 +2445,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_STABLE
https://toolchains.bootlin.com/
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_UCLIBC_BLEEDING_EDGE
- bool "openrisc uclibc bleeding-edge 2021.11-4"
+ bool "openrisc uclibc bleeding-edge 2021.11-5"
depends on BR2_or1k
select BR2_TOOLCHAIN_GCC_AT_LEAST_11
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
@@ -2468,7 +2468,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_UCLIBC_BLEEDING_EDGE
https://toolchains.bootlin.com/
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_UCLIBC_STABLE
- bool "openrisc uclibc stable 2021.11-4"
+ bool "openrisc uclibc stable 2021.11-5"
depends on BR2_or1k
select BR2_TOOLCHAIN_GCC_AT_LEAST_10
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
index 638130d8b8..8819782ac5 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
@@ -192,14 +192,14 @@ sha256 30d82c7ca41a0df9931a29a46ed881f21a889e9e59baf04e820c6679be87a7fb mips64
sha256 5c2dc11062f4817e81a328b12ab30be486b7e68c7c876eb45fffca72332a8804 nios2--glibc--bleeding-edge-2021.11-1.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/nios2/tarballs/nios2--glibc--stable-2021.11-1.sha256
sha256 f6f37f1e551edda0251ece8d906ed720bd8ec45da9d4b3e1d13721bdc9ef2882 nios2--glibc--stable-2021.11-1.tar.bz2
-# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--musl--bleeding-edge-2021.11-4.sha256
-sha256 9100a143a2f96c46d4d593fb25f4cab4a2efc61371f12bd1a686fbd52ee64c63 openrisc--musl--bleeding-edge-2021.11-4.tar.bz2
-# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--musl--stable-2021.11-4.sha256
-sha256 72fce2be59c18a5b3a02f51ebb83119a0f3d29ab7f2d5cd560038ff6f94f137a openrisc--musl--stable-2021.11-4.tar.bz2
-# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--uclibc--bleeding-edge-2021.11-4.sha256
-sha256 ffbdedf741bcfeadaf0c52ac09af83b24eedca2e9a5fc563127c5fdbd10c79a6 openrisc--uclibc--bleeding-edge-2021.11-4.tar.bz2
-# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--uclibc--stable-2021.11-4.sha256
-sha256 082ec406a6a516d582a092e63f9078e200a1e32dc24d47928f90c09b1e61819b openrisc--uclibc--stable-2021.11-4.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--musl--bleeding-edge-2021.11-5.sha256
+sha256 03f46c8fdded0002a2a04749bcf86136ec26a841654bf9fdc14575cc510739c6 openrisc--musl--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--musl--stable-2021.11-5.sha256
+sha256 409e4a7473125e7de7c8b0e6bc1cb971d53e63ac057e9a19102e4ce1467f442a openrisc--musl--stable-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--uclibc--bleeding-edge-2021.11-5.sha256
+sha256 9028d4e526f9e805b021791443805541a179eaf2e47a2af4dfbefb2021e44e9f openrisc--uclibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs/openrisc--uclibc--stable-2021.11-5.sha256
+sha256 f07d8e465f7e94e55330cfb55bbaf9fc27e4bb7b688271ead60a15aec3dbbf76 openrisc--uclibc--stable-2021.11-5.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc-440fp/tarballs/powerpc-440fp--glibc--bleeding-edge-2021.11-1.sha256
sha256 53afdbe1e48d0c60d560db8d17042a99288661fe10eebbfcfec4e56a6c2ca594 powerpc-440fp--glibc--bleeding-edge-2021.11-1.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc-440fp/tarballs/powerpc-440fp--glibc--stable-2021.11-1.sha256
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
index f28592272c..64ae44f364 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
@@ -583,25 +583,25 @@ TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/relea
endif
ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_BLEEDING_EDGE),y)
-TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-4
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = openrisc--musl--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs
endif
ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_MUSL_STABLE),y)
-TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-4
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = openrisc--musl--stable-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs
endif
ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_UCLIBC_BLEEDING_EDGE),y)
-TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-4
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = openrisc--uclibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs
endif
ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_OPENRISC_UCLIBC_STABLE),y)
-TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-4
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = openrisc--uclibc--stable-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/openrisc/tarballs
endif
--
2.34.1
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 02/16] support/scripts/gen-bootlin-toolchains: add support for new x86-64 toolchains
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
2022-01-24 23:00 ` [Buildroot] [PATCH 01/16] toolchain/toolchain-external/toolchain-external-bootlin: re-update OpenRISC toolchains Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 03/16] toolchain/toolchain-external/toolchain-external-bootlin: update with " Thomas Petazzoni
` (14 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
Following the merge of
d6ce2a16814fd96a45888a774da6a4db74cd540a ("arch/Config.in.x86: add
option for -march=x86-64") and
eeace1cc13ce09a0c88ce177465b836d6eb58298 ("arch/Config.in.x86: add support for
x86-64-v2, x86-64-v3, x86-64-v4"), bootlin.toolchains.com now provides
toolchains targetting the x86-64, x86-64-v2, x86-64-v3 and x86-64-v4
architecture variants.
This commits modifies gen-bootlin-toolchains to support these
toolchains. It should be noted that the description for the x86-64-v3
and x86-64-v4 toolchains are for now the same, as Buildroot doesn't
yet have the options to describe the extra features that x86-64-v4
expects to find on the hardware platform.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
support/scripts/gen-bootlin-toolchains | 48 ++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/support/scripts/gen-bootlin-toolchains b/support/scripts/gen-bootlin-toolchains
index f160a44152..a42ddb4097 100755
--- a/support/scripts/gen-bootlin-toolchains
+++ b/support/scripts/gen-bootlin-toolchains
@@ -178,6 +178,54 @@ arches = {
'conditions': ['BR2_sparc', 'BR2_sparc_v8'],
'prefix': 'sparc',
},
+ 'x86-64': {
+ 'conditions': ['BR2_x86_64',
+ 'BR2_X86_CPU_HAS_MMX',
+ 'BR2_X86_CPU_HAS_SSE',
+ 'BR2_X86_CPU_HAS_SSE2'],
+ 'test_options': ['BR2_x86_64', 'BR2_x86_x86_64'],
+ 'prefix': 'x86_64',
+ },
+ 'x86-64-v2': {
+ 'conditions': ['BR2_x86_64',
+ 'BR2_X86_CPU_HAS_MMX',
+ 'BR2_X86_CPU_HAS_SSE',
+ 'BR2_X86_CPU_HAS_SSE2',
+ 'BR2_X86_CPU_HAS_SSE3',
+ 'BR2_X86_CPU_HAS_SSSE3',
+ 'BR2_X86_CPU_HAS_SSE4',
+ 'BR2_X86_CPU_HAS_SSE42'],
+ 'test_options': ['BR2_x86_64', 'BR2_x86_x86_64_v2'],
+ 'prefix': 'x86_64',
+ },
+ 'x86-64-v3': {
+ 'conditions': ['BR2_x86_64',
+ 'BR2_X86_CPU_HAS_MMX',
+ 'BR2_X86_CPU_HAS_SSE',
+ 'BR2_X86_CPU_HAS_SSE2',
+ 'BR2_X86_CPU_HAS_SSE3',
+ 'BR2_X86_CPU_HAS_SSSE3',
+ 'BR2_X86_CPU_HAS_SSE4',
+ 'BR2_X86_CPU_HAS_SSE42',
+ 'BR2_X86_CPU_HAS_AVX',
+ 'BR2_X86_CPU_HAS_AVX2'],
+ 'test_options': ['BR2_x86_64', 'BR2_x86_x86_64_v3'],
+ 'prefix': 'x86_64',
+ },
+ 'x86-64-v4': {
+ 'conditions': ['BR2_x86_64',
+ 'BR2_X86_CPU_HAS_MMX',
+ 'BR2_X86_CPU_HAS_SSE',
+ 'BR2_X86_CPU_HAS_SSE2',
+ 'BR2_X86_CPU_HAS_SSE3',
+ 'BR2_X86_CPU_HAS_SSSE3',
+ 'BR2_X86_CPU_HAS_SSE4',
+ 'BR2_X86_CPU_HAS_SSE42',
+ 'BR2_X86_CPU_HAS_AVX',
+ 'BR2_X86_CPU_HAS_AVX2'],
+ 'test_options': ['BR2_x86_64', 'BR2_x86_x86_64_v4'],
+ 'prefix': 'x86_64',
+ },
'x86-64-core-i7': {
'conditions': ['BR2_x86_64',
'BR2_X86_CPU_HAS_MMX',
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 03/16] toolchain/toolchain-external/toolchain-external-bootlin: update with new x86-64 toolchains
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
2022-01-24 23:00 ` [Buildroot] [PATCH 01/16] toolchain/toolchain-external/toolchain-external-bootlin: re-update OpenRISC toolchains Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 02/16] support/scripts/gen-bootlin-toolchains: add support for new x86-64 toolchains Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 04/16] arch/Config.in.x86: drastically simplify the BR2_ARCH definition Thomas Petazzoni
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List
Cc: Thomas De Schampheleire, Romain Naour, Giulio Benetti,
Yann E. MORIN, Thomas Petazzoni
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
.../tests/toolchain/test_external_bootlin.py | 225 +++++++++
.../Config.in.options | 446 ++++++++++++++++++
.../toolchain-external-bootlin.hash | 30 ++
.../toolchain-external-bootlin.mk | 90 ++++
4 files changed, 791 insertions(+)
diff --git a/support/testing/tests/toolchain/test_external_bootlin.py b/support/testing/tests/toolchain/test_external_bootlin.py
index 5e908b957e..cf6174303e 100644
--- a/support/testing/tests/toolchain/test_external_bootlin.py
+++ b/support/testing/tests/toolchain/test_external_bootlin.py
@@ -2362,6 +2362,231 @@ class TestExternalToolchainBootlinSparcv8UclibcStable(TestExternalToolchain):
TestExternalToolchain.common_check(self)
+class TestExternalToolchainBootlinX8664GlibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664GlibcStable(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_STABLE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664MuslBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664MuslStable(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_STABLE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664UclibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664UclibcStable(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_STABLE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v2GlibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v2=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_GLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v2MuslBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v2=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_MUSL_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v2UclibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v2=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_UCLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v3GlibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v3=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_GLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v3MuslBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v3=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_MUSL_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v3UclibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v3=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_UCLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v4GlibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v4=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_GLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v4MuslBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v4=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_MUSL_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
+class TestExternalToolchainBootlinX8664v4UclibcBleedingEdge(TestExternalToolchain):
+ config = """
+ BR2_x86_64=y
+ BR2_x86_x86_64_v4=y
+ BR2_TOOLCHAIN_EXTERNAL=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
+ BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_UCLIBC_BLEEDING_EDGE=y
+ # BR2_TARGET_ROOTFS_TAR is not set
+ """
+ toolchain_prefix = "x86_64-linux"
+
+ def test_run(self):
+ TestExternalToolchain.common_check(self)
+
+
class TestExternalToolchainBootlinX8664corei7GlibcBleedingEdge(TestExternalToolchain):
config = """
BR2_x86_64=y
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
index 55b6d4c786..42cad21d71 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
@@ -37,6 +37,10 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_ARCH_SUPPORTS
default y if BR2_sh && BR2_sh4aeb
default y if BR2_sparc64 && BR2_sparc_v9
default y if BR2_sparc && BR2_sparc_v8
+ default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2
+ default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42
+ default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42 && BR2_X86_CPU_HAS_AVX && BR2_X86_CPU_HAS_AVX2
+ default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42 && BR2_X86_CPU_HAS_AVX && BR2_X86_CPU_HAS_AVX2
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42
default y if BR2_i386 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3
default y if BR2_i386 && !BR2_x86_i486 && !BR2_x86_i586 && !BR2_x86_x1000
@@ -3791,6 +3795,448 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_SPARCV8_UCLIBC_STABLE
https://toolchains.bootlin.com/
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_BLEEDING_EDGE
+ bool "x86-64 glibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_USE_MMU
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ glibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_STABLE
+ bool "x86-64 glibc stable 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_USE_MMU
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_10
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ glibc C library. This is a stable version, which means it
+ is using stable and proven versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_BLEEDING_EDGE
+ bool "x86-64 musl bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_USE_MMU
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_MUSL
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ musl C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_STABLE
+ bool "x86-64 musl stable 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_USE_MMU
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_10
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_MUSL
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ musl C library. This is a stable version, which means it is
+ using stable and proven versions of gcc, gdb and binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_BLEEDING_EDGE
+ bool "x86-64 uclibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_USE_WCHAR
+ select BR2_ENABLE_LOCALE
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_UCLIBC
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ uclibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_STABLE
+ bool "x86-64 uclibc stable 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_10
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9
+ select BR2_USE_WCHAR
+ select BR2_ENABLE_LOCALE
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_UCLIBC
+ help
+ Bootlin toolchain for the x86-64 architecture, using the
+ uclibc C library. This is a stable version, which means it
+ is using stable and proven versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_GLIBC_BLEEDING_EDGE
+ bool "x86-64-v2 glibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_USE_MMU
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ help
+ Bootlin toolchain for the x86-64-v2 architecture, using the
+ glibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_MUSL_BLEEDING_EDGE
+ bool "x86-64-v2 musl bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_USE_MMU
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_MUSL
+ help
+ Bootlin toolchain for the x86-64-v2 architecture, using the
+ musl C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_UCLIBC_BLEEDING_EDGE
+ bool "x86-64-v2 uclibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_USE_WCHAR
+ select BR2_ENABLE_LOCALE
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_UCLIBC
+ help
+ Bootlin toolchain for the x86-64-v2 architecture, using the
+ uclibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_GLIBC_BLEEDING_EDGE
+ bool "x86-64-v3 glibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_USE_MMU
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ help
+ Bootlin toolchain for the x86-64-v3 architecture, using the
+ glibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_MUSL_BLEEDING_EDGE
+ bool "x86-64-v3 musl bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_USE_MMU
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_MUSL
+ help
+ Bootlin toolchain for the x86-64-v3 architecture, using the
+ musl C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_UCLIBC_BLEEDING_EDGE
+ bool "x86-64-v3 uclibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_USE_WCHAR
+ select BR2_ENABLE_LOCALE
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_UCLIBC
+ help
+ Bootlin toolchain for the x86-64-v3 architecture, using the
+ uclibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_GLIBC_BLEEDING_EDGE
+ bool "x86-64-v4 glibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_USE_MMU
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ help
+ Bootlin toolchain for the x86-64-v4 architecture, using the
+ glibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_MUSL_BLEEDING_EDGE
+ bool "x86-64-v4 musl bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_USE_MMU
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_MUSL
+ help
+ Bootlin toolchain for the x86-64-v4 architecture, using the
+ musl C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
+config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_UCLIBC_BLEEDING_EDGE
+ bool "x86-64-v4 uclibc bleeding-edge 2021.11-5"
+ depends on BR2_x86_64
+ depends on BR2_X86_CPU_HAS_MMX
+ depends on BR2_X86_CPU_HAS_SSE
+ depends on BR2_X86_CPU_HAS_SSE2
+ depends on BR2_X86_CPU_HAS_SSE3
+ depends on BR2_X86_CPU_HAS_SSSE3
+ depends on BR2_X86_CPU_HAS_SSE4
+ depends on BR2_X86_CPU_HAS_SSE42
+ depends on BR2_X86_CPU_HAS_AVX
+ depends on BR2_X86_CPU_HAS_AVX2
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_11
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
+ select BR2_USE_WCHAR
+ select BR2_ENABLE_LOCALE
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_DEBUG
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS
+ select BR2_TOOLCHAIN_HAS_THREADS_NPTL
+ select BR2_TOOLCHAIN_EXTERNAL_UCLIBC
+ help
+ Bootlin toolchain for the x86-64-v4 architecture, using the
+ uclibc C library. This is a bleeding-edge version, which
+ means it is using the latest versions of gcc, gdb and
+ binutils.
+
+ https://toolchains.bootlin.com/
+
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_CORE_I7_GLIBC_BLEEDING_EDGE
bool "x86-64-core-i7 glibc bleeding-edge 2021.11-1"
depends on BR2_x86_64
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
index 8819782ac5..6542694033 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.hash
@@ -306,6 +306,36 @@ sha256 0ef307f6c91733ee82ce65801768013f7e6220b605f4e152158cb55b4f983582 sparc6
sha256 3c85420becb7caa84a9a229483f3f2d7158eb66817acdfa5d5700c3a05436cba sparcv8--uclibc--bleeding-edge-2021.11-3.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/sparcv8/tarballs/sparcv8--uclibc--stable-2021.11-1.sha256
sha256 f6d35e33338b26e71403b4c6d3944ab561f2a6e9b801ab33fbb401b4722044dd sparcv8--uclibc--stable-2021.11-1.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--glibc--bleeding-edge-2021.11-5.sha256
+sha256 024fd8edc91b9bfd643f8cf94e3f3ff2a6457aea654d10ef3516db8c3d94d5f5 x86-64--glibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--glibc--stable-2021.11-5.sha256
+sha256 6fe812add925493ea0841365f1fb7ca17fd9224bab61a731063f7f12f3a621b0 x86-64--glibc--stable-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--musl--bleeding-edge-2021.11-5.sha256
+sha256 468e6b73146595923fe87980a30adb54cd78f4c1e2f228e1a2c9bb705ea4243d x86-64--musl--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--musl--stable-2021.11-5.sha256
+sha256 2943617f6537ca195a66fb9db4a801a5dd1c108741c400d530d558d06908dd75 x86-64--musl--stable-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--uclibc--bleeding-edge-2021.11-5.sha256
+sha256 4aa8b8e2806d6fc87ba64ccec0a59b8a2fb5d157cda006d893e3f2264b7f0f10 x86-64--uclibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs/x86-64--uclibc--stable-2021.11-5.sha256
+sha256 e68fd1b23f4a5c5132f2122e4012c17eb24e5179b2ff45bb793a27ac30dd454f x86-64--uclibc--stable-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs/x86-64-v2--glibc--bleeding-edge-2021.11-5.sha256
+sha256 af20cf98ce937f298e0958e16793bb4c7b08236bc69ab11574a4266cccc3823d x86-64-v2--glibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs/x86-64-v2--musl--bleeding-edge-2021.11-5.sha256
+sha256 17add21a0337d2f7d0d79d1f21db88098c3474920d71f902be46e8995eb86d35 x86-64-v2--musl--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs/x86-64-v2--uclibc--bleeding-edge-2021.11-5.sha256
+sha256 b3ef49012af9fc9c2c8a44b0a20722be69b518cec5db06e48480291fc28aefe0 x86-64-v2--uclibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs/x86-64-v3--glibc--bleeding-edge-2021.11-5.sha256
+sha256 244d4afab02b9c54c76385657d26798515331d7d4fa90928315366f31b9cc39e x86-64-v3--glibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs/x86-64-v3--musl--bleeding-edge-2021.11-5.sha256
+sha256 551cff1b6425e2a6ced7b7ad032fba49b43ed095faae38d1842260ac0b5d6dbf x86-64-v3--musl--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs/x86-64-v3--uclibc--bleeding-edge-2021.11-5.sha256
+sha256 30188f50adef711b55ac1d5be7218e0d6ee4200ddb8660e4d4971a9cefe22f91 x86-64-v3--uclibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs/x86-64-v4--glibc--bleeding-edge-2021.11-5.sha256
+sha256 0cd2de7c4103aa8cf47b72dc71146eb3bf7742a18d56c93128340ab3f4175804 x86-64-v4--glibc--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs/x86-64-v4--musl--bleeding-edge-2021.11-5.sha256
+sha256 e159da16459e0f0d06a9a7467d5121202ab95e2fa6bf8abffdc0008c72fe9b07 x86-64-v4--musl--bleeding-edge-2021.11-5.tar.bz2
+# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs/x86-64-v4--uclibc--bleeding-edge-2021.11-5.sha256
+sha256 984f011d170d3e46322ae4a110c86ebf995598d877f410201b3fb3d86e25dac2 x86-64-v4--uclibc--bleeding-edge-2021.11-5.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-core-i7/tarballs/x86-64-core-i7--glibc--bleeding-edge-2021.11-1.sha256
sha256 a3dbfcd3347a72ca344ae77882f929615776ea9b1b058eeea0a0915e7db89b69 x86-64-core-i7--glibc--bleeding-edge-2021.11-1.tar.bz2
# From https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-core-i7/tarballs/x86-64-core-i7--glibc--stable-2021.11-1.sha256
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
index 64ae44f364..fb19ef2909 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/toolchain-external-bootlin.mk
@@ -924,6 +924,96 @@ TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = sparcv8--uclibc--stable-$(TOOLCHAIN_EXTERNAL
TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/sparcv8/tarballs
endif
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--glibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_GLIBC_STABLE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--glibc--stable-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--musl--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_MUSL_STABLE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--musl--stable-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--uclibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_UCLIBC_STABLE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64--uclibc--stable-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_GLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v2--glibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_MUSL_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v2--musl--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V2_UCLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v2--uclibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v2/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_GLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v3--glibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_MUSL_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v3--musl--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V3_UCLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v3--uclibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v3/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_GLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v4--glibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_MUSL_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v4--musl--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs
+endif
+
+ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_UCLIBC_BLEEDING_EDGE),y)
+TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-5
+TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-v4--uclibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
+TOOLCHAIN_EXTERNAL_BOOTLIN_SITE = https://toolchains.bootlin.com/downloads/releases/toolchains/x86-64-v4/tarballs
+endif
+
ifeq ($(BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_CORE_I7_GLIBC_BLEEDING_EDGE),y)
TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION = 2021.11-1
TOOLCHAIN_EXTERNAL_BOOTLIN_SOURCE = x86-64-core-i7--glibc--bleeding-edge-$(TOOLCHAIN_EXTERNAL_BOOTLIN_VERSION).tar.bz2
--
2.34.1
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 04/16] arch/Config.in.x86: drastically simplify the BR2_ARCH definition
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (2 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 03/16] toolchain/toolchain-external/toolchain-external-bootlin: update with " Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 05/16] arch/Config.in.x86: add "newer" names for several Intel x86 CPU variants Thomas Petazzoni
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
The BR2_ARCH definition is like this:
* i486 for the i486 platform
* i586 for a small number of platforms
* i686 for all other x86 platforms when used in 32-bit, but we
enumerate their entire list
* x86_64 for all x86 64-bit platforms
The list for i686 is long and needs to be extended everytime a new
platform is added, with no added value.
So this commit simplifies that by replacing this long list with just:
default "i686" if BR2_i386
This works because Kconfig guarantees us that if an i386 platform
matches an earlier case (i486 or one of the i586 platforms), the i486
and i586 earlier in the list will match.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 30 ++++++------------------------
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 0ba9ecbcea..a330d72f1d 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -311,30 +311,12 @@ config BR2_ARCH
default "i686" if BR2_x86_c32
default "i586" if BR2_x86_winchip_c6
default "i586" if BR2_x86_winchip2
- default "i686" if BR2_x86_i686
- default "i686" if BR2_x86_pentium2
- default "i686" if BR2_x86_pentium3
- default "i686" if BR2_x86_pentium4
- default "i686" if BR2_x86_pentium_m
- default "i686" if BR2_x86_pentiumpro
- default "i686" if BR2_x86_prescott
- default "i686" if BR2_x86_nocona && BR2_i386
- default "i686" if BR2_x86_core2 && BR2_i386
- default "i686" if BR2_x86_corei7 && BR2_i386
- default "i686" if BR2_x86_westmere && BR2_i386
- default "i686" if BR2_x86_corei7_avx && BR2_i386
- default "i686" if BR2_x86_core_avx2 && BR2_i386
- default "i686" if BR2_x86_atom && BR2_i386
- default "i686" if BR2_x86_silvermont && BR2_i386
- default "i686" if BR2_x86_opteron && BR2_i386
- default "i686" if BR2_x86_opteron_sse3 && BR2_i386
- default "i686" if BR2_x86_barcelona && BR2_i386
- default "i686" if BR2_x86_jaguar && BR2_i386
- default "i686" if BR2_x86_steamroller && BR2_i386
- default "i686" if BR2_x86_k6
- default "i686" if BR2_x86_k6_2
- default "i686" if BR2_x86_athlon
- default "i686" if BR2_x86_athlon_4
+ # We use the property of Kconfig that the first match of a
+ # list of default will be chosen. So the following entry will
+ # not match for all BR2_i386=y configurations, but only the
+ # ones that didn't match any of the previous cases (i486,
+ # i586).
+ default "i686" if BR2_i386
default "x86_64" if BR2_x86_64
config BR2_ENDIAN
--
2.34.1
_______________________________________________
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https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 05/16] arch/Config.in.x86: add "newer" names for several Intel x86 CPU variants
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (3 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 04/16] arch/Config.in.x86: drastically simplify the BR2_ARCH definition Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 06/16] arch/Config.in.x86: westmere and silvermont were added in gcc 4.9 Thomas Petazzoni
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
In gcc commit d3c11974032e21121a051d423a1d71097edf752f ("Use proper
Intel processor names for -march=/-mtune="), which was merged in gcc
4.9, the following replacements were made:
* corei7 -> nehalem
* corei7-avx -> sandybridge
* core-avx-i -> ivybridge
* core-avx2 -> haswell
* atom -> bonnel
* slm -> silvermont
So this commit marks the Buildroot options BR2_x86_corei7,
BR2_x86_corei7_avx, BR2_x86_core_avx2 and BR2_x86_atom as deprecated,
and adds the four corresponding options with the newer names.
Note that the older options are still kept because the new option
names are only supported starting gcc 4.9, and we theoretically still
supports targets gcc as old as gcc 4.3.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 57 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index a330d72f1d..4beb11662d 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -174,6 +174,19 @@ config BR2_x86_corei7
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
+ help
+ This option is deprecated. Since gcc 4.9, the gcc option
+ "nehalem" is preferred. Use BR2_x86_nehalem instead.
+config BR2_x86_nehalem
+ bool "nehalem"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_westmere
bool "westmere"
select BR2_X86_CPU_HAS_MMX
@@ -193,6 +206,20 @@ config BR2_x86_corei7_avx
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
+ help
+ This option is deprecated. Since gcc 4.9, the gcc option
+ "sandybridge" is preferred. Use BR2_x86_sandybridge instead.
+config BR2_x86_sandybridge
+ bool "sandybridge"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_core_avx2
bool "core-avx2"
select BR2_X86_CPU_HAS_MMX
@@ -204,6 +231,21 @@ config BR2_x86_core_avx2
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
+ help
+ This option is deprecated. Since gcc 4.9, the gcc option
+ "haswell" is preferred. Use BR2_x86_haswell instead.
+config BR2_x86_haswell
+ bool "haswell"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_atom
bool "atom"
select BR2_X86_CPU_HAS_MMX
@@ -211,6 +253,17 @@ config BR2_x86_atom
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
+ help
+ This option is deprecated. Since gcc 4.9, the gcc option
+ "bonnel" is preferred. Use BR2_x86_bonnel instead.
+config BR2_x86_bonnel
+ bool "bonnel"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_silvermont
bool "silvermont"
select BR2_X86_CPU_HAS_MMX
@@ -341,9 +394,13 @@ config BR2_GCC_TARGET_ARCH
default "nocona" if BR2_x86_nocona
default "core2" if BR2_x86_core2
default "corei7" if BR2_x86_corei7
+ default "nehalem" if BR2_x86_nehalem
default "corei7-avx" if BR2_x86_corei7_avx
+ default "sandybridge" if BR2_x86_sandybridge
default "core-avx2" if BR2_x86_core_avx2
+ default "haswell" if BR2_x86_haswell
default "atom" if BR2_x86_atom
+ default "bonnel" if BR2_x86_bonnel
default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
default "k8" if BR2_x86_opteron
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 06/16] arch/Config.in.x86: westmere and silvermont were added in gcc 4.9
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (4 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 05/16] arch/Config.in.x86: add "newer" names for several Intel x86 CPU variants Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 07/16] arch/Config.in.x86: add broadwell Intel CPU variant Thomas Petazzoni
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
These were added in gcc commit
d3c11974032e21121a051d423a1d71097edf752f ("Use proper Intel processor
names for -march=/-mtune=") which was merged in gcc 4.9.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 4beb11662d..0aae26799c 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -196,6 +196,7 @@ config BR2_x86_westmere
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_corei7_avx
bool "corei7-avx"
select BR2_X86_CPU_HAS_MMX
@@ -273,6 +274,7 @@ config BR2_x86_silvermont
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
--
2.34.1
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2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (5 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 06/16] arch/Config.in.x86: westmere and silvermont were added in gcc 4.9 Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 08/16] arch/Config.in.x86: add skylake CPU variants Thomas Petazzoni
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
It was added in gcc 4.9.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 0aae26799c..d5d84715b8 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -247,6 +247,18 @@ config BR2_x86_haswell
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
+config BR2_x86_broadwell
+ bool "broadwell"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_atom
bool "atom"
select BR2_X86_CPU_HAS_MMX
@@ -401,6 +413,7 @@ config BR2_GCC_TARGET_ARCH
default "sandybridge" if BR2_x86_sandybridge
default "core-avx2" if BR2_x86_core_avx2
default "haswell" if BR2_x86_haswell
+ default "broadwell" if BR2_x86_broadwell
default "atom" if BR2_x86_atom
default "bonnel" if BR2_x86_bonnel
default "westmere" if BR2_x86_westmere
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 08/16] arch/Config.in.x86: add skylake CPU variants
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (6 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 07/16] arch/Config.in.x86: add broadwell Intel CPU variant Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 09/16] arch/Config.in.x86: x86-64-v4 implies AVX512 Thomas Petazzoni
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
Both skylake and skylake-avx512 were added in gcc 6.x. According to
https://en.wikipedia.org/wiki/Skylake_(microarchitecture) the early
Skylake processors indeed did not have AVX512 support, while the later
ones did, hence the separate gcc options.
Due to this being the first CPU we support with AVX512, this commit
adds BR2_X86_CPU_HAS_AVX512.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index d5d84715b8..6b18580ae4 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -19,6 +19,8 @@ config BR2_X86_CPU_HAS_AVX
bool
config BR2_X86_CPU_HAS_AVX2
bool
+config BR2_X86_CPU_HAS_AVX512
+ bool
choice
prompt "Target Architecture Variant"
@@ -259,6 +261,18 @@ config BR2_x86_broadwell
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
+config BR2_x86_skylake
+ bool "skylake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_x86_atom
bool "atom"
select BR2_X86_CPU_HAS_MMX
@@ -287,6 +301,19 @@ config BR2_x86_silvermont
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
+config BR2_x86_skylake_avx512
+ bool "skylake-avx512"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
@@ -414,10 +441,12 @@ config BR2_GCC_TARGET_ARCH
default "core-avx2" if BR2_x86_core_avx2
default "haswell" if BR2_x86_haswell
default "broadwell" if BR2_x86_broadwell
+ default "skylake" if BR2_x86_skylake
default "atom" if BR2_x86_atom
default "bonnel" if BR2_x86_bonnel
default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
+ default "skylake-avx512" if BR2_x86_skylake_avx512
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 09/16] arch/Config.in.x86: x86-64-v4 implies AVX512
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (7 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 08/16] arch/Config.in.x86: add skylake CPU variants Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 10/16] support/scripts/gen-bootlin-toolchains: add missing BR2_X86_CPU_HAS_AVX512 condition for x86-64-v4 Thomas Petazzoni
` (7 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
Now that we have BR2_X86_CPU_HAS_AVX512, we can use it to fix the
x86-64-v4 definition, which implies AVX512 support according to
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 6b18580ae4..2034fb3bb7 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -146,6 +146,7 @@ config BR2_x86_x86_64_v4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
help
This option corresponds to the x86-64-v4 micro-architecture
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 10/16] support/scripts/gen-bootlin-toolchains: add missing BR2_X86_CPU_HAS_AVX512 condition for x86-64-v4
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (8 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 09/16] arch/Config.in.x86: x86-64-v4 implies AVX512 Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 11/16] toolchain/toolchain-external/toolchain-external-bootlin: regenerate with AVX512 condition for x86-64-v4 toolchain Thomas Petazzoni
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
The x86-64-v4 toolchain assumes availability of AVX512, as per the
definition of the x86-64-v4 "standard".
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
support/scripts/gen-bootlin-toolchains | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/support/scripts/gen-bootlin-toolchains b/support/scripts/gen-bootlin-toolchains
index a42ddb4097..dc173fa949 100755
--- a/support/scripts/gen-bootlin-toolchains
+++ b/support/scripts/gen-bootlin-toolchains
@@ -222,7 +222,8 @@ arches = {
'BR2_X86_CPU_HAS_SSE4',
'BR2_X86_CPU_HAS_SSE42',
'BR2_X86_CPU_HAS_AVX',
- 'BR2_X86_CPU_HAS_AVX2'],
+ 'BR2_X86_CPU_HAS_AVX2',
+ 'BR2_X86_CPU_HAS_AVX512'],
'test_options': ['BR2_x86_64', 'BR2_x86_x86_64_v4'],
'prefix': 'x86_64',
},
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 11/16] toolchain/toolchain-external/toolchain-external-bootlin: regenerate with AVX512 condition for x86-64-v4 toolchain
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (9 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 10/16] support/scripts/gen-bootlin-toolchains: add missing BR2_X86_CPU_HAS_AVX512 condition for x86-64-v4 Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 12/16] arch/Config.in.x86: add cannonlake, icelake-client, icelake-server CPU variants Thomas Petazzoni
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List
Cc: Thomas De Schampheleire, Giulio Benetti, Romain Naour,
Yann E. MORIN, Thomas Petazzoni
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
.../toolchain-external-bootlin/Config.in.options | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
index 42cad21d71..4b4404620c 100644
--- a/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
+++ b/toolchain/toolchain-external/toolchain-external-bootlin/Config.in.options
@@ -40,7 +40,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_ARCH_SUPPORTS
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42 && BR2_X86_CPU_HAS_AVX && BR2_X86_CPU_HAS_AVX2
- default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42 && BR2_X86_CPU_HAS_AVX && BR2_X86_CPU_HAS_AVX2
+ default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42 && BR2_X86_CPU_HAS_AVX && BR2_X86_CPU_HAS_AVX2 && BR2_X86_CPU_HAS_AVX512
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42
default y if BR2_i386 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3
default y if BR2_i386 && !BR2_x86_i486 && !BR2_x86_i586 && !BR2_x86_x1000
@@ -4152,6 +4152,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_GLIBC_BLEEDING_EDGE
depends on BR2_X86_CPU_HAS_SSE42
depends on BR2_X86_CPU_HAS_AVX
depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_X86_CPU_HAS_AVX512
depends on BR2_USE_MMU
depends on !BR2_STATIC_LIBS
select BR2_TOOLCHAIN_GCC_AT_LEAST_11
@@ -4185,6 +4186,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_MUSL_BLEEDING_EDGE
depends on BR2_X86_CPU_HAS_SSE42
depends on BR2_X86_CPU_HAS_AVX
depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_X86_CPU_HAS_AVX512
depends on BR2_USE_MMU
select BR2_TOOLCHAIN_GCC_AT_LEAST_11
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
@@ -4217,6 +4219,7 @@ config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_X86_64_V4_UCLIBC_BLEEDING_EDGE
depends on BR2_X86_CPU_HAS_SSE42
depends on BR2_X86_CPU_HAS_AVX
depends on BR2_X86_CPU_HAS_AVX2
+ depends on BR2_X86_CPU_HAS_AVX512
select BR2_TOOLCHAIN_GCC_AT_LEAST_11
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
select BR2_USE_WCHAR
--
2.34.1
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2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (10 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 11/16] toolchain/toolchain-external/toolchain-external-bootlin: regenerate with AVX512 condition for x86-64-v4 toolchain Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 13/16] arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake, tigerlake " Thomas Petazzoni
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
These were added in gcc 8.x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 2034fb3bb7..e9c55bb319 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -315,6 +315,45 @@ config BR2_x86_skylake_avx512
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_x86_cannonlake
+ bool "cannonlake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
+config BR2_x86_icelake_client
+ bool "icelake-client"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
+config BR2_x86_icelake_server
+ bool "icelake-server"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
@@ -448,6 +487,9 @@ config BR2_GCC_TARGET_ARCH
default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
default "skylake-avx512" if BR2_x86_skylake_avx512
+ default "cannonlake" if BR2_x86_cannonlake
+ default "icelake-client" if BR2_x86_icelake_client
+ default "icelake-server" if BR2_x86_icelake_server
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 13/16] arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake, tigerlake CPU variants
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (11 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 12/16] arch/Config.in.x86: add cannonlake, icelake-client, icelake-server CPU variants Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 14/16] arch/Config.in.x86: add cooperlake CPU variant Thomas Petazzoni
` (3 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
These were added in gcc 9.x. The goldmont, goldmont-plus and tremont
are for the low-power CPUs. While cascadelake and tigerlake are for
the high-end ones.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 61 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index e9c55bb319..dffc9a74d3 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -302,6 +302,36 @@ config BR2_x86_silvermont
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
+config BR2_x86_goldmont
+ bool "goldmont"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
+config BR2_x86_goldmont_plus
+ bool "goldmont-plus"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
+config BR2_x86_tremont
+ bool "tremont"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_skylake_avx512
bool "skylake-avx512"
select BR2_X86_CPU_HAS_MMX
@@ -354,6 +384,32 @@ config BR2_x86_icelake_server
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
+config BR2_x86_cascadelake
+ bool "cascadelake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
+config BR2_x86_tigerlake
+ bool "tigerlake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
@@ -486,10 +542,15 @@ config BR2_GCC_TARGET_ARCH
default "bonnel" if BR2_x86_bonnel
default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
+ default "goldmont" if BR2_x86_goldmont
+ default "goldmont-plus" if BR2_x86_goldmont_plus
+ default "tremont" if BR2_x86_tremont
default "skylake-avx512" if BR2_x86_skylake_avx512
default "cannonlake" if BR2_x86_cannonlake
default "icelake-client" if BR2_x86_icelake_client
default "icelake-server" if BR2_x86_icelake_server
+ default "cascadelake" if BR2_x86_cascadelake
+ default "tigerlake" if BR2_x86_tigerlake
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 14/16] arch/Config.in.x86: add cooperlake CPU variant
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (12 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 13/16] arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake, tigerlake " Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 15/16] arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake Thomas Petazzoni
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
It was added in gcc 10.x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index dffc9a74d3..08837b7cea 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -397,6 +397,19 @@ config BR2_x86_cascadelake
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
+config BR2_x86_cooperlake
+ bool "cooperlake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
config BR2_x86_tigerlake
bool "tigerlake"
select BR2_X86_CPU_HAS_MMX
@@ -550,6 +563,7 @@ config BR2_GCC_TARGET_ARCH
default "icelake-client" if BR2_x86_icelake_client
default "icelake-server" if BR2_x86_icelake_server
default "cascadelake" if BR2_x86_cascadelake
+ default "cooperlake" if BR2_x86_cooperlake
default "tigerlake" if BR2_x86_tigerlake
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 15/16] arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (13 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 14/16] arch/Config.in.x86: add cooperlake CPU variant Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-24 23:01 ` [Buildroot] [PATCH 16/16] arch/Config.in.x86: indicate how the CPU variants are ordered Thomas Petazzoni
2022-01-25 7:58 ` [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Yann E. MORIN
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
These were added in gcc 11.x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 08837b7cea..cae5502051 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -423,6 +423,45 @@ config BR2_x86_tigerlake
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
+config BR2_x86_sapphirerapids
+ bool "sapphirerapids"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
+config BR2_x86_alderlake
+ bool "alderlake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
+config BR2_x86_rocketlake
+ bool "rocketlake"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
+ select BR2_X86_CPU_HAS_AVX
+ select BR2_X86_CPU_HAS_AVX2
+ select BR2_X86_CPU_HAS_AVX512
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
@@ -565,6 +604,9 @@ config BR2_GCC_TARGET_ARCH
default "cascadelake" if BR2_x86_cascadelake
default "cooperlake" if BR2_x86_cooperlake
default "tigerlake" if BR2_x86_tigerlake
+ default "sapphirerapids" if BR2_x86_sapphirerapids
+ default "alderlake" if BR2_x86_alderlake
+ default "rocketlake" if BR2_x86_rocketlake
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [Buildroot] [PATCH 16/16] arch/Config.in.x86: indicate how the CPU variants are ordered
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (14 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 15/16] arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake Thomas Petazzoni
@ 2022-01-24 23:01 ` Thomas Petazzoni
2022-01-25 7:58 ` [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Yann E. MORIN
16 siblings, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-24 23:01 UTC (permalink / raw)
To: Buildroot List; +Cc: Yann E. MORIN, Thomas Petazzoni
They are loosely ordered according to the ordering of the gcc
documentation. It is not entirely correct as the generic x86-64,
x86-64-v2, x86-64-v3 and x86-64-v4 are listed before i386 in the gcc
documentation, but this nevertheless gives a good explanation for the
overall ordering of the list.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/Config.in.x86 | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index cae5502051..27f2bfcd4c 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -22,6 +22,9 @@ config BR2_X86_CPU_HAS_AVX2
config BR2_X86_CPU_HAS_AVX512
bool
+# This list of CPU architecture variant is (loosely) ordered according
+# to the gcc documentation at
+# https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/x86-Options.html
choice
prompt "Target Architecture Variant"
default BR2_x86_i586 if BR2_i386
--
2.34.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates
2022-01-24 23:00 [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Thomas Petazzoni
` (15 preceding siblings ...)
2022-01-24 23:01 ` [Buildroot] [PATCH 16/16] arch/Config.in.x86: indicate how the CPU variants are ordered Thomas Petazzoni
@ 2022-01-25 7:58 ` Yann E. MORIN
2022-01-25 9:11 ` Thomas Petazzoni
16 siblings, 1 reply; 20+ messages in thread
From: Yann E. MORIN @ 2022-01-25 7:58 UTC (permalink / raw)
To: Thomas Petazzoni; +Cc: Buildroot List
Thomas, All,
On 2022-01-25 00:00 +0100, Thomas Petazzoni spake thusly:
[--SNIP--]
> Thomas Petazzoni (16):
> toolchain/toolchain-external/toolchain-external-bootlin: re-update
> OpenRISC toolchains
> support/scripts/gen-bootlin-toolchains: add support for new x86-64
> toolchains
> toolchain/toolchain-external/toolchain-external-bootlin: update with
> new x86-64 toolchains
> arch/Config.in.x86: drastically simplify the BR2_ARCH definition
> arch/Config.in.x86: add "newer" names for several Intel x86 CPU
> variants
I was wondering if we should expand the prompt to include the fact that
they are deprecated, or specific to gcc versions before 4.9... But
whatever I tried was ugly or confusing, so I just left it as-is.
Full series applied to master, thanks.
Regards,
Yann E. MORIN.
> arch/Config.in.x86: westmere and silvermont were added in gcc 4.9
> arch/Config.in.x86: add broadwell Intel CPU variant
> arch/Config.in.x86: add skylake CPU variants
> arch/Config.in.x86: x86-64-v4 implies AVX512
> support/scripts/gen-bootlin-toolchains: add missing
> BR2_X86_CPU_HAS_AVX512 condition for x86-64-v4
> toolchain/toolchain-external/toolchain-external-bootlin: regenerate
> with AVX512 condition for x86-64-v4 toolchain
> arch/Config.in.x86: add cannonlake, icelake-client, icelake-server CPU
> variants
> arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake,
> tigerlake CPU variants
> arch/Config.in.x86: add cooperlake CPU variant
> arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake
> arch/Config.in.x86: indicate how the CPU variants are ordered
>
> arch/Config.in.x86 | 294 ++++++++++-
> support/scripts/gen-bootlin-toolchains | 49 ++
> .../tests/toolchain/test_external_bootlin.py | 225 +++++++++
> .../Config.in.options | 457 +++++++++++++++++-
> .../toolchain-external-bootlin.hash | 46 +-
> .../toolchain-external-bootlin.mk | 98 +++-
> 6 files changed, 1129 insertions(+), 40 deletions(-)
>
> --
> 2.34.1
>
--
.-----------------.--------------------.------------------.--------------------.
| Yann E. MORIN | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
| +33 662 376 056 | Software Designer | \ / CAMPAIGN | ___ |
| +33 561 099 427 `------------.-------: X AGAINST | \e/ There is no |
| http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL | v conspiracy. |
'------------------------------^-------^------------------^--------------------'
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates
2022-01-25 7:58 ` [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates Yann E. MORIN
@ 2022-01-25 9:11 ` Thomas Petazzoni
2022-01-25 17:01 ` Yann E. MORIN
0 siblings, 1 reply; 20+ messages in thread
From: Thomas Petazzoni @ 2022-01-25 9:11 UTC (permalink / raw)
To: Yann E. MORIN; +Cc: Buildroot List
Hello,
On Tue, 25 Jan 2022 08:58:17 +0100
"Yann E. MORIN" <yann.morin.1998@free.fr> wrote:
> > Thomas Petazzoni (16):
> > toolchain/toolchain-external/toolchain-external-bootlin: re-update
> > OpenRISC toolchains
> > support/scripts/gen-bootlin-toolchains: add support for new x86-64
> > toolchains
> > toolchain/toolchain-external/toolchain-external-bootlin: update with
> > new x86-64 toolchains
> > arch/Config.in.x86: drastically simplify the BR2_ARCH definition
> > arch/Config.in.x86: add "newer" names for several Intel x86 CPU
> > variants
>
> I was wondering if we should expand the prompt to include the fact that
> they are deprecated, or specific to gcc versions before 4.9... But
> whatever I tried was ugly or confusing, so I just left it as-is.
Originally, I was hoping to simply remove them, and add
Config.in.legacy entries for these options, selecting the new ones. But
alas, before gcc 4.9, the "new" names didn't exist.
> Full series applied to master, thanks.
Wow, thanks \o/
Thomas
--
Thomas Petazzoni, co-owner and CEO, Bootlin
Embedded Linux and Kernel engineering and training
https://bootlin.com
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Buildroot] [PATCH 00/16] Bootlin toolchain updates and x86 updates
2022-01-25 9:11 ` Thomas Petazzoni
@ 2022-01-25 17:01 ` Yann E. MORIN
0 siblings, 0 replies; 20+ messages in thread
From: Yann E. MORIN @ 2022-01-25 17:01 UTC (permalink / raw)
To: Thomas Petazzoni; +Cc: Buildroot List
Thomas, All,
On 2022-01-25 10:11 +0100, Thomas Petazzoni spake thusly:
> On Tue, 25 Jan 2022 08:58:17 +0100
> "Yann E. MORIN" <yann.morin.1998@free.fr> wrote:
> > > Thomas Petazzoni (16):
[--SNIP--]
> > > arch/Config.in.x86: add "newer" names for several Intel x86 CPU
> > > variants
> > I was wondering if we should expand the prompt to include the fact that
> > they are deprecated, or specific to gcc versions before 4.9... But
> > whatever I tried was ugly or confusing, so I just left it as-is.
> Originally, I was hoping to simply remove them, and add
> Config.in.legacy entries for these options, selecting the new ones. But
> alas, before gcc 4.9, the "new" names didn't exist.
Yeah, I was wondering why we would not add them to legacy, then I read
the commit log. ;-)
But in the end, I believe legacy should be doable, albeit a bit ugly.
In legacy (only two entries used as example):
config BR2_x86_corei7
bool "corei7 has been renamed to nehalem"
select BR2_LEGACY
config BR2_x86_atom
bool "atom has been renamed to bonnel"
select BR2_LEGACY
And then in the choice in arch/Config.in.x86:
choice
bool "Target Architecture Variant"
default BR2_x86_nehalem if BR2_x86_corei7 # legacy
default BR2_x86_bonnel if BR2_x86_atom # legacy
default default BR2_x86_i586 if BR2_i386
depends on BR2_i386 || BR2_x86_64 # [0]
[...]
config BR2_x86_nehalem
bool "nehalem (corei7 for gcc < 4.9)"
config BR2_x86_bonnel
bool "bonnel (previously: atom)"
endchoice
config BR2_GCC_TARGET_ARCH
[...]
default "nehalem" if BR2_x86_nehalem && BR2_TOOLCHAIN_GCC_AT_LEAST_4_9
default "corei7" if BR2_x86_nehalem # Legacy fallback
default "bonnel" if BR2_x86_bonnel && BR2_TOOLCHAIN_GCC_AT_LEAST_4_9
default "atom" if BR2_x86_bonnel # Legacy fallback
[...]
This is a bit ugly, but a minor inconvenience. Note how I wrote two
different prompts: it's just for illustration purposes, we'll need to
settle on one or the other (or something else).
[0] this dependency is superfluous, as the whole of arch/Config.in.x86
is already conditionally included with this same condition from
arch/Config.in
Regards,
Yann E. MORIN.
--
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| http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL | v conspiracy. |
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