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From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v2 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations
Date: Fri, 28 Jan 2022 10:55:00 +0530	[thread overview]
Message-ID: <20220128052505.859518-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com>

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f72527fcb347..9786fc641436 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -621,8 +621,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(target);
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index b5d30ea92292..6fd8b3cbec1b 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -89,8 +89,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1


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WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v2 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations
Date: Fri, 28 Jan 2022 10:55:00 +0530	[thread overview]
Message-ID: <20220128052505.859518-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com>

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f72527fcb347..9786fc641436 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -621,8 +621,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(target);
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index b5d30ea92292..6fd8b3cbec1b 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -89,8 +89,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1


  reply	other threads:[~2022-01-28  5:26 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-28  5:24 [PATCH v2 0/6] RISC-V IPI Improvements Anup Patel
2022-01-28  5:24 ` Anup Patel
2022-01-28  5:25 ` Anup Patel [this message]
2022-01-28  5:25   ` [PATCH v2 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2022-01-28  5:25 ` [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode Anup Patel
2022-01-28  5:25   ` Anup Patel
2022-02-17 15:12   ` Marc Zyngier
2022-02-17 15:12     ` Marc Zyngier
2022-02-19  3:38     ` Anup Patel
2022-02-19  3:38       ` Anup Patel
2022-02-19  9:32       ` Marc Zyngier
2022-02-19  9:32         ` Marc Zyngier
2022-02-19 13:03         ` Anup Patel
2022-02-19 13:03           ` Anup Patel
2022-02-21  9:07           ` Marc Zyngier
2022-02-21  9:07             ` Marc Zyngier
2022-02-21  9:38             ` Anup Patel
2022-02-21  9:38               ` Anup Patel
2022-02-19 14:51         ` Jessica Clarke
2022-02-19 14:51           ` Jessica Clarke
2022-02-21  9:25           ` Marc Zyngier
2022-02-21  9:25             ` Marc Zyngier
2022-02-21  9:44             ` Anup Patel
2022-02-21  9:44               ` Anup Patel
2022-01-28  5:25 ` [PATCH v2 3/6] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2022-01-28  5:25   ` Anup Patel
2022-01-28  5:25 ` [PATCH v2 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2022-01-28  5:25   ` Anup Patel
2022-01-28  5:25 ` [PATCH v2 5/6] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2022-01-28  5:25   ` Anup Patel
2022-01-28  5:25 ` [PATCH v2 6/6] RISC-V: Use IPIs for remote icache " Anup Patel
2022-01-28  5:25   ` Anup Patel

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