Re: [PATCH 6/6] spi: tegra210-quad: combined sequence mode

[kernel test robot <lkp@intel.com>]

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Hi Krishna,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on v5.17-rc2 next-20220204]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Krishna-Yarlagadda/Tegra-QUAD-SPI-combined-sequence-mode/20220204-183224
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: s390-allyesconfig (https://download.01.org/0day-ci/archive/20220204/202202042150.HorCV3rE-lkp(a)intel.com/config)
compiler: s390-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/7b66ae189feb38fc460bc1eaf1374f82fd0eb893
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Krishna-Yarlagadda/Tegra-QUAD-SPI-combined-sequence-mode/20220204-183224
        git checkout 7b66ae189feb38fc460bc1eaf1374f82fd0eb893
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=s390 SHELL=/bin/bash drivers/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/spi/spi-tegra210-quad.c: In function 'tegra_qspi_combined_seq_xfer':
>> drivers/spi/spi-tegra210-quad.c:1052:27: warning: variable 'len' set but not used [-Wunused-but-set-variable]
    1052 |         u8 cmd_value = 0, len = 0, val = 0;
         |                           ^~~
>> drivers/spi/spi-tegra210-quad.c:1044:13: warning: variable 'single_xfer' set but not used [-Wunused-but-set-variable]
    1044 |         int single_xfer;
         |             ^~~~~~~~~~~
   drivers/spi/spi-tegra210-quad.c: In function 'tegra_qspi_probe':
   drivers/spi/spi-tegra210-quad.c:1528:9: warning: ignoring return value of 'device_reset' declared with attribute 'warn_unused_result' [-Wunused-result]
    1528 |         device_reset(tqspi->dev);
         |         ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/spi/spi-tegra210-quad.c: In function 'tegra_qspi_handle_error':
   drivers/spi/spi-tegra210-quad.c:989:9: warning: ignoring return value of 'device_reset' declared with attribute 'warn_unused_result' [-Wunused-result]
     989 |         device_reset(tqspi->dev);
         |         ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/spi/spi-tegra210-quad.c: In function 'tegra_qspi_combined_seq_xfer':
   drivers/spi/spi-tegra210-quad.c:1133:33: warning: ignoring return value of 'device_reset' declared with attribute 'warn_unused_result' [-Wunused-result]
    1133 |                                 device_reset(tqspi->dev);
         |                                 ^~~~~~~~~~~~~~~~~~~~~~~~


vim +/len +1052 drivers/spi/spi-tegra210-quad.c

  1039	
  1040	static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
  1041						struct spi_message *msg)
  1042	{
  1043		bool is_first_msg = true;
> 1044		int single_xfer;
  1045		struct spi_transfer *xfer;
  1046		struct spi_device *spi = msg->spi;
  1047		u8 transfer_phase = 0;
  1048		u32 cmd1 = 0, dma_ctl = 0;
  1049		int ret;
  1050		u32 address_value = 0;
  1051		u32 cmd_config = 0, addr_config = 0;
> 1052		u8 cmd_value = 0, len = 0, val = 0;
  1053	
  1054		/* Enable Combined sequence mode */
  1055		val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
  1056		val |= QSPI_CMB_SEQ_EN;
  1057		tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
  1058		single_xfer = list_is_singular(&msg->transfers);
  1059		/* Process individual transfer list */
  1060		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  1061			if (transfer_phase == CMD_TRANSFER) {
  1062				/* X1 SDR mode */
  1063				cmd_config = tegra_qspi_cmd_config(false, 0,
  1064								   xfer->len);
  1065				cmd_value = *((const u8 *)(xfer->tx_buf));
  1066	
  1067			} else if (transfer_phase == ADDR_TRANSFER) {
  1068				len = xfer->len;
  1069				/* X1 SDR mode */
  1070				addr_config = tegra_qspi_addr_config(false, 0,
  1071								     xfer->len);
  1072				address_value = *((const u32 *)(xfer->tx_buf));
  1073			} else {
  1074				/* Program Command, Address value in register */
  1075				tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
  1076				tegra_qspi_writel(tqspi, address_value,
  1077						  QSPI_CMB_SEQ_ADDR);
  1078				/* Program Command and Address config in register */
  1079				tegra_qspi_writel(tqspi, cmd_config,
  1080						  QSPI_CMB_SEQ_CMD_CFG);
  1081				tegra_qspi_writel(tqspi, addr_config,
  1082						  QSPI_CMB_SEQ_ADDR_CFG);
  1083	
  1084				reinit_completion(&tqspi->xfer_completion);
  1085				cmd1 = tegra_qspi_setup_transfer_one(spi, xfer,
  1086								     is_first_msg);
  1087				ret = tegra_qspi_start_transfer_one(spi, xfer,
  1088								    cmd1);
  1089	
  1090				if (ret < 0) {
  1091					dev_err(tqspi->dev, "Failed to start transfer-one: %d\n",
  1092						ret);
  1093					return ret;
  1094				}
  1095	
  1096				is_first_msg = false;
  1097				ret = wait_for_completion_timeout
  1098						(&tqspi->xfer_completion,
  1099						QSPI_DMA_TIMEOUT);
  1100	
  1101				if (WARN_ON(ret == 0)) {
  1102					dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n",
  1103						ret);
  1104					if (tqspi->is_curr_dma_xfer &&
  1105					    (tqspi->cur_direction & DATA_DIR_TX))
  1106						dmaengine_terminate_all
  1107							(tqspi->tx_dma_chan);
  1108	
  1109					if (tqspi->is_curr_dma_xfer &&
  1110					    (tqspi->cur_direction & DATA_DIR_RX))
  1111						dmaengine_terminate_all
  1112							(tqspi->rx_dma_chan);
  1113	
  1114					/* Abort transfer by resetting pio/dma bit */
  1115					if (!tqspi->is_curr_dma_xfer) {
  1116						cmd1 = tegra_qspi_readl
  1117								(tqspi,
  1118								 QSPI_COMMAND1);
  1119						cmd1 &= ~QSPI_PIO;
  1120						tegra_qspi_writel
  1121								(tqspi, cmd1,
  1122								 QSPI_COMMAND1);
  1123					} else {
  1124						dma_ctl = tegra_qspi_readl
  1125								(tqspi,
  1126								 QSPI_DMA_CTL);
  1127						dma_ctl &= ~QSPI_DMA_EN;
  1128						tegra_qspi_writel(tqspi, dma_ctl,
  1129								  QSPI_DMA_CTL);
  1130					}
  1131	
  1132					/* Reset controller if timeout happens */
  1133					device_reset(tqspi->dev);
  1134					ret = -EIO;
  1135					goto exit;
  1136				}
  1137	
  1138				if (tqspi->tx_status ||  tqspi->rx_status) {
  1139					dev_err(tqspi->dev, "QSPI Transfer failed\n");
  1140					tqspi->tx_status = 0;
  1141					tqspi->rx_status = 0;
  1142					ret = -EIO;
  1143					goto exit;
  1144				}
  1145			}
  1146			msg->actual_length += xfer->len;
  1147			transfer_phase++;
  1148		}
  1149	
  1150	exit:
  1151		msg->status = ret;
  1152	
  1153		return ret;
  1154	}
  1155	

---
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