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From: Jonathan Cameron via iommu <iommu@lists.linux-foundation.org>
To: Yicong Yang <yangyicong@hisilicon.com>
Cc: mark.rutland@arm.com, prime.zeng@huawei.com,
	alexander.shishkin@linux.intel.com, linux-pci@vger.kernel.org,
	linuxarm@huawei.com, will@kernel.org, daniel.thompson@linaro.org,
	peterz@infradead.org, mingo@redhat.com, helgaas@kernel.org,
	liuqi115@huawei.com, mike.leach@linaro.org,
	suzuki.poulose@arm.com, coresight@lists.linaro.org,
	acme@kernel.org, zhangshaokun@hisilicon.com,
	linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org,
	gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	iommu@lists.linux-foundation.org, leo.yan@linaro.org,
	robin.murphy@arm.com
Subject: Re: [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device
Date: Mon, 7 Feb 2022 11:49:11 +0000	[thread overview]
Message-ID: <20220207114911.0000127e@Huawei.com> (raw)
In-Reply-To: <20220124131118.17887-5-yangyicong@hisilicon.com>

On Mon, 24 Jan 2022 21:11:14 +0800
Yicong Yang <yangyicong@hisilicon.com> wrote:

> Add tune function for the HiSilicon Tune and Trace device. The interface
> of tune is exposed through sysfs attributes of PTT PMU device.
> 
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>

A few trivial things inline, but looks good in general to me.
With those tidied up
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


> ---
>  drivers/hwtracing/ptt/hisi_ptt.c | 154 +++++++++++++++++++++++++++++++
>  drivers/hwtracing/ptt/hisi_ptt.h |  19 ++++
>  2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c
> index 2994354e690b..b11e702eb506 100644
> --- a/drivers/hwtracing/ptt/hisi_ptt.c
> +++ b/drivers/hwtracing/ptt/hisi_ptt.c
> @@ -21,6 +21,159 @@
>  
>  #include "hisi_ptt.h"
>  
> +static int hisi_ptt_wait_tuning_finish(struct hisi_ptt *hisi_ptt)
> +{
> +	u32 val;
> +
> +	return readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TUNING_INT_STAT,
> +				  val, !(val & HISI_PTT_TUNING_INT_STAT_MASK),
> +				  HISI_PTT_WAIT_POLL_INTERVAL_US,
> +				  HISI_PTT_WAIT_TIMEOUT_US);
> +}
> +
> +static int hisi_ptt_tune_data_get(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 *data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	/* Write all 1 to indicates it's the read process */
> +	writel(~0UL, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);

Just to check, this is includes the bits above the DATA_VAL_MASK?
Fine if so, just seems odd to define a field but then write 
parts of the register that aren't part of that field.

> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +	reg &= HISI_PTT_TUNING_DATA_VAL_MASK;
> +	*data = (u16)reg;

As below, prefer a FIELD_GET() for this.

> +
> +	return 0;
> +}
> +
> +static int hisi_ptt_tune_data_set(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	reg = data;
Given you defined HISI_PTT_TUNING_DATA_VAL_MASK why not use it here

writel(FIELD_PREP(..), ...)? 

> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	return 0;
> +}
> +


_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Yicong Yang <yangyicong@hisilicon.com>
Cc: <gregkh@linuxfoundation.org>, <helgaas@kernel.org>,
	<alexander.shishkin@linux.intel.com>, <lorenzo.pieralisi@arm.com>,
	<will@kernel.org>, <mark.rutland@arm.com>,
	<mathieu.poirier@linaro.org>, <suzuki.poulose@arm.com>,
	<mike.leach@linaro.org>, <leo.yan@linaro.org>,
	<daniel.thompson@linaro.org>, <joro@8bytes.org>,
	<john.garry@huawei.com>, <shameerali.kolothum.thodi@huawei.com>,
	<robin.murphy@arm.com>, <peterz@infradead.org>,
	<mingo@redhat.com>, <acme@kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-pci@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<iommu@lists.linux-foundation.org>, <prime.zeng@huawei.com>,
	<liuqi115@huawei.com>, <zhangshaokun@hisilicon.com>,
	<linuxarm@huawei.com>, <song.bao.hua@hisilicon.com>
Subject: Re: [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device
Date: Mon, 7 Feb 2022 11:49:11 +0000	[thread overview]
Message-ID: <20220207114911.0000127e@Huawei.com> (raw)
In-Reply-To: <20220124131118.17887-5-yangyicong@hisilicon.com>

On Mon, 24 Jan 2022 21:11:14 +0800
Yicong Yang <yangyicong@hisilicon.com> wrote:

> Add tune function for the HiSilicon Tune and Trace device. The interface
> of tune is exposed through sysfs attributes of PTT PMU device.
> 
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>

A few trivial things inline, but looks good in general to me.
With those tidied up
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


> ---
>  drivers/hwtracing/ptt/hisi_ptt.c | 154 +++++++++++++++++++++++++++++++
>  drivers/hwtracing/ptt/hisi_ptt.h |  19 ++++
>  2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c
> index 2994354e690b..b11e702eb506 100644
> --- a/drivers/hwtracing/ptt/hisi_ptt.c
> +++ b/drivers/hwtracing/ptt/hisi_ptt.c
> @@ -21,6 +21,159 @@
>  
>  #include "hisi_ptt.h"
>  
> +static int hisi_ptt_wait_tuning_finish(struct hisi_ptt *hisi_ptt)
> +{
> +	u32 val;
> +
> +	return readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TUNING_INT_STAT,
> +				  val, !(val & HISI_PTT_TUNING_INT_STAT_MASK),
> +				  HISI_PTT_WAIT_POLL_INTERVAL_US,
> +				  HISI_PTT_WAIT_TIMEOUT_US);
> +}
> +
> +static int hisi_ptt_tune_data_get(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 *data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	/* Write all 1 to indicates it's the read process */
> +	writel(~0UL, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);

Just to check, this is includes the bits above the DATA_VAL_MASK?
Fine if so, just seems odd to define a field but then write 
parts of the register that aren't part of that field.

> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +	reg &= HISI_PTT_TUNING_DATA_VAL_MASK;
> +	*data = (u16)reg;

As below, prefer a FIELD_GET() for this.

> +
> +	return 0;
> +}
> +
> +static int hisi_ptt_tune_data_set(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	reg = data;
Given you defined HISI_PTT_TUNING_DATA_VAL_MASK why not use it here

writel(FIELD_PREP(..), ...)? 

> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	return 0;
> +}
> +



WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Yicong Yang <yangyicong@hisilicon.com>
Cc: <gregkh@linuxfoundation.org>, <helgaas@kernel.org>,
	<alexander.shishkin@linux.intel.com>, <lorenzo.pieralisi@arm.com>,
	<will@kernel.org>, <mark.rutland@arm.com>,
	<mathieu.poirier@linaro.org>, <suzuki.poulose@arm.com>,
	<mike.leach@linaro.org>, <leo.yan@linaro.org>,
	<daniel.thompson@linaro.org>, <joro@8bytes.org>,
	<john.garry@huawei.com>, <shameerali.kolothum.thodi@huawei.com>,
	<robin.murphy@arm.com>, <peterz@infradead.org>,
	<mingo@redhat.com>, <acme@kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-pci@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<iommu@lists.linux-foundation.org>, <prime.zeng@huawei.com>,
	<liuqi115@huawei.com>, <zhangshaokun@hisilicon.com>,
	 <linuxarm@huawei.com>, <song.bao.hua@hisilicon.com>
Subject: Re: [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device
Date: Mon, 7 Feb 2022 11:49:11 +0000	[thread overview]
Message-ID: <20220207114911.0000127e@Huawei.com> (raw)
In-Reply-To: <20220124131118.17887-5-yangyicong@hisilicon.com>

On Mon, 24 Jan 2022 21:11:14 +0800
Yicong Yang <yangyicong@hisilicon.com> wrote:

> Add tune function for the HiSilicon Tune and Trace device. The interface
> of tune is exposed through sysfs attributes of PTT PMU device.
> 
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>

A few trivial things inline, but looks good in general to me.
With those tidied up
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


> ---
>  drivers/hwtracing/ptt/hisi_ptt.c | 154 +++++++++++++++++++++++++++++++
>  drivers/hwtracing/ptt/hisi_ptt.h |  19 ++++
>  2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c
> index 2994354e690b..b11e702eb506 100644
> --- a/drivers/hwtracing/ptt/hisi_ptt.c
> +++ b/drivers/hwtracing/ptt/hisi_ptt.c
> @@ -21,6 +21,159 @@
>  
>  #include "hisi_ptt.h"
>  
> +static int hisi_ptt_wait_tuning_finish(struct hisi_ptt *hisi_ptt)
> +{
> +	u32 val;
> +
> +	return readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TUNING_INT_STAT,
> +				  val, !(val & HISI_PTT_TUNING_INT_STAT_MASK),
> +				  HISI_PTT_WAIT_POLL_INTERVAL_US,
> +				  HISI_PTT_WAIT_TIMEOUT_US);
> +}
> +
> +static int hisi_ptt_tune_data_get(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 *data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	/* Write all 1 to indicates it's the read process */
> +	writel(~0UL, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);

Just to check, this is includes the bits above the DATA_VAL_MASK?
Fine if so, just seems odd to define a field but then write 
parts of the register that aren't part of that field.

> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +	reg &= HISI_PTT_TUNING_DATA_VAL_MASK;
> +	*data = (u16)reg;

As below, prefer a FIELD_GET() for this.

> +
> +	return 0;
> +}
> +
> +static int hisi_ptt_tune_data_set(struct hisi_ptt *hisi_ptt,
> +				  u32 event, u16 data)
> +{
> +	u32 reg;
> +
> +	reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +	reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
> +	reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
> +			  event);
> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
> +
> +	reg = data;
Given you defined HISI_PTT_TUNING_DATA_VAL_MASK why not use it here

writel(FIELD_PREP(..), ...)? 

> +	writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
> +
> +	if (hisi_ptt_wait_tuning_finish(hisi_ptt))
> +		return -ETIMEDOUT;
> +
> +	return 0;
> +}
> +



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-02-07 11:49 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-24 13:11 [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
2022-01-24 13:11 ` Yicong Yang
2022-01-24 13:11 ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 1/8] hwtracing: Add trace function " Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-07 11:42   ` Jonathan Cameron via iommu
2022-02-07 11:42     ` Jonathan Cameron
2022-02-07 11:42     ` Jonathan Cameron
2022-02-08 11:07     ` Yicong Yang via iommu
2022-02-08 11:07       ` Yicong Yang
2022-02-08 11:07       ` Yicong Yang
2022-02-14 12:51       ` Yicong Yang via iommu
2022-02-14 12:51         ` Yicong Yang
2022-02-14 12:51         ` Yicong Yang
2022-02-07 18:11   ` John Garry via iommu
2022-02-07 18:11     ` John Garry
2022-02-07 18:11     ` John Garry
2022-02-08  8:57     ` Yicong Yang via iommu
2022-02-08  8:57       ` Yicong Yang
2022-02-08  8:57       ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 2/8] hisi_ptt: Register PMU device for PTT trace Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-07 11:42   ` Jonathan Cameron via iommu
2022-02-07 11:42     ` Jonathan Cameron
2022-02-07 11:42     ` Jonathan Cameron
2022-02-08  7:41     ` Yicong Yang via iommu
2022-02-08  7:41       ` Yicong Yang
2022-02-08  7:41       ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 3/8] hisi_ptt: Add support for dynamically updating the filter list Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-07 11:49   ` Jonathan Cameron via iommu [this message]
2022-02-07 11:49     ` Jonathan Cameron
2022-02-07 11:49     ` Jonathan Cameron
2022-02-08  7:08     ` Yicong Yang via iommu
2022-02-08  7:08       ` Yicong Yang
2022-02-08  7:08       ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 5/8] perf tool: Add support for HiSilicon PCIe Tune and Trace device driver Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-07 11:55   ` Jonathan Cameron via iommu
2022-02-07 11:55     ` Jonathan Cameron
2022-02-07 11:55     ` Jonathan Cameron
2022-01-24 13:11 ` [PATCH v3 6/8] docs: Add HiSilicon PTT device driver documentation Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-07 12:12   ` Jonathan Cameron via iommu
2022-02-07 12:12     ` Jonathan Cameron
2022-02-07 12:12     ` Jonathan Cameron
2022-02-08 11:09     ` Yicong Yang via iommu
2022-02-08 11:09       ` Yicong Yang
2022-02-08 11:09       ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 7/8] MAINTAINERS: Add maintainer for HiSilicon PTT driver Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity Yicong Yang via iommu
2022-01-24 13:11   ` Yicong Yang
2022-01-24 13:11   ` Yicong Yang
2022-02-08  8:05   ` John Garry via iommu
2022-02-08  8:05     ` John Garry
2022-02-08  8:05     ` John Garry
2022-02-08 11:21     ` Yicong Yang via iommu
2022-02-08 11:21       ` Yicong Yang
2022-02-08 11:21       ` Yicong Yang
2022-02-08 11:56       ` John Garry via iommu
2022-02-08 11:56         ` John Garry
2022-02-08 11:56         ` John Garry
2022-02-08 12:20         ` Yicong Yang via iommu
2022-02-08 12:20           ` Yicong Yang
2022-02-08 12:20           ` Yicong Yang
2022-02-14 12:55   ` Yicong Yang via iommu
2022-02-14 12:55     ` Yicong Yang
2022-02-14 12:55     ` Yicong Yang
2022-02-15 13:00     ` Will Deacon
2022-02-15 13:00       ` Will Deacon
2022-02-15 13:00       ` Will Deacon
2022-02-15 13:30       ` Robin Murphy
2022-02-15 13:30         ` Robin Murphy
2022-02-15 13:30         ` Robin Murphy
2022-02-15 13:42         ` Will Deacon
2022-02-15 13:42           ` Will Deacon
2022-02-15 13:42           ` Will Deacon
2022-02-15 14:29           ` Robin Murphy
2022-02-15 14:29             ` Robin Murphy
2022-02-15 14:29             ` Robin Murphy
2022-02-16  9:35             ` Yicong Yang via iommu
2022-02-16  9:35               ` Yicong Yang
2022-02-16  9:35               ` Yicong Yang
2022-02-07  9:40 ` [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
2022-02-07  9:40   ` Yicong Yang
2022-02-07  9:40   ` Yicong Yang

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