From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Suzuki Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
Anshuman Khandual <anshuman.khandual@arm.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>
Subject: [PATCH 5.15 2/5] arm64: Add Cortex-A510 CPU part definition
Date: Wed, 9 Feb 2022 20:14:27 +0100 [thread overview]
Message-ID: <20220209191250.067270808@linuxfoundation.org> (raw)
In-Reply-To: <20220209191249.980911721@linuxfoundation.org>
From: Anshuman Khandual <anshuman.khandual@arm.com>
commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 upstream.
Add the CPU Partnumbers for the new Arm designs.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,7 @@
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
+#define ARM_CPU_PART_CORTEX_A510 0xD46
#define APM_CPU_PART_POTENZA 0x000
@@ -113,6 +114,7 @@
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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WARNING: multiple messages have this Message-ID (diff)
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Suzuki Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
Anshuman Khandual <anshuman.khandual@arm.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>
Subject: [PATCH 5.15 2/5] arm64: Add Cortex-A510 CPU part definition
Date: Wed, 9 Feb 2022 20:14:27 +0100 [thread overview]
Message-ID: <20220209191250.067270808@linuxfoundation.org> (raw)
In-Reply-To: <20220209191249.980911721@linuxfoundation.org>
From: Anshuman Khandual <anshuman.khandual@arm.com>
commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 upstream.
Add the CPU Partnumbers for the new Arm designs.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,7 @@
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
+#define ARM_CPU_PART_CORTEX_A510 0xD46
#define APM_CPU_PART_POTENZA 0x000
@@ -113,6 +114,7 @@
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
next prev parent reply other threads:[~2022-02-09 19:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 19:14 [PATCH 5.15 0/5] 5.15.23-rc1 review Greg Kroah-Hartman
2022-02-09 19:14 ` [PATCH 5.15 1/5] moxart: fix potential use-after-free on remove path Greg Kroah-Hartman
2022-02-09 19:14 ` Greg Kroah-Hartman [this message]
2022-02-09 19:14 ` [PATCH 5.15 2/5] arm64: Add Cortex-A510 CPU part definition Greg Kroah-Hartman
2022-02-09 19:14 ` [PATCH 5.15 3/5] KVM: s390: Return error on SIDA memop on normal guest Greg Kroah-Hartman
2022-02-09 19:14 ` [PATCH 5.15 4/5] ksmbd: fix SMB 3.11 posix extension mount failure Greg Kroah-Hartman
2022-02-09 19:14 ` [PATCH 5.15 5/5] crypto: api - Move cryptomgr soft dependency into algapi Greg Kroah-Hartman
2022-02-10 0:54 ` [PATCH 5.15 0/5] 5.15.23-rc1 review Fox Chen
2022-02-10 0:57 ` Shuah Khan
2022-02-10 7:47 ` Ron Economos
2022-02-10 8:33 ` Jon Hunter
2022-02-10 10:49 ` Naresh Kamboju
2022-02-10 16:01 ` Sudip Mukherjee
2022-02-10 17:54 ` Florian Fainelli
2022-02-10 21:01 ` Guenter Roeck
2022-02-11 5:13 ` Bagas Sanjaya
2022-02-11 6:12 ` Slade Watkins
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