* [PATCH 01/11] drm/amd/display: reset lane settings after each PHY repeater LT
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 02/11] drm/amd/display: Fix for dmub outbox notification enable Jasdeep Dhillon
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, roman.li,
Meenakshikumar Somasundaram, solomon.chiu, Aurabindo.Pillai,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, Sung Joon Kim,
agustin.gutierrez, pavle.kotarac
From: Sung Joon Kim <sungkim@amd.com>
[why]
In LTTPR non-transparent mode, we need
to reset the cached lane settings before performing
link training on the next PHY repeater. Otherwise,
the cached lane settings will be used for the next
clock recovery e.g. VS = MAX (3) which should not be
the case according to the DP specs. We expect to use
minimum lane settings on each clock recovery sequence.
[how]
Reset DPCD and HW lane settings on each repeater LT.
Set training pattern to 0 for the repeater that failed LT
at the proper place.
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cd9c31b5e55d..d62b59d52ba8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2230,22 +2230,27 @@ static enum link_training_result dp_perform_8b_10b_link_training(
repeater_id--) {
status = perform_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
- if (status != LINK_TRAINING_SUCCESS)
+ if (status != LINK_TRAINING_SUCCESS) {
+ repeater_training_done(link, repeater_id);
break;
+ }
status = perform_channel_equalization_sequence(link,
link_res,
lt_settings,
repeater_id);
+ repeater_training_done(link, repeater_id);
+
if (status != LINK_TRAINING_SUCCESS)
break;
- repeater_training_done(link, repeater_id);
+ for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+ lt_settings->dpcd_lane_settings[lane].raw = 0;
+ lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
+ lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
+ }
}
-
- for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
- lt_settings->dpcd_lane_settings[lane].raw = 0;
}
if (status == LINK_TRAINING_SUCCESS) {
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/11] drm/amd/display: Fix for dmub outbox notification enable
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 01/11] drm/amd/display: reset lane settings after each PHY repeater LT Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 03/11] drm/amd/display: dsc mst re-compute pbn for changes on hub Jasdeep Dhillon
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, roman.li,
Meenakshikumar Somasundaram, solomon.chiu, Aurabindo.Pillai,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
[Why]
Currently driver enables dmub outbox notification before oubox ISR is
registered. During boot scenario, sometimes dmub issues hpd outbox
message before driver registers ISR and those messages are missed.
[How]
Enable dmub outbox notification after outbox ISR is registered. Also,
restructured outbox enable code to call from dm layer and renamed APIs.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 66 +++++++++++++++++--
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../gpu/drm/amd/display/dc/dce/dmub_outbox.c | 25 +++----
.../gpu/drm/amd/display/dc/dce/dmub_outbox.h | 4 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 --
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 2 +-
6 files changed, 80 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 467f606ba2c7..7ebd9ba5f3e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -76,6 +76,8 @@
#include "dc_trace.h"
+#include "dce/dmub_outbox.h"
+
#define CTX \
dc->ctx
@@ -3703,13 +3705,23 @@ void dc_hardware_release(struct dc *dc)
}
#endif
-/**
- * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
- * @dc: dc structure
+/*
+ *****************************************************************************
+ * Function: dc_is_dmub_outbox_supported -
+ *
+ * @brief
+ * Checks whether DMUB FW supports outbox notifications, if supported
+ * DM should register outbox interrupt prior to actually enabling interrupts
+ * via dc_enable_dmub_outbox
*
- * Returns: True to enable dmub notifications, False otherwise
+ * @param
+ * [in] dc: dc structure
+ *
+ * @return
+ * True if DMUB FW supports outbox notifications, False otherwise
+ *****************************************************************************
*/
-bool dc_enable_dmub_notifications(struct dc *dc)
+bool dc_is_dmub_outbox_supported(struct dc *dc)
{
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
@@ -3724,6 +3736,48 @@ bool dc_enable_dmub_notifications(struct dc *dc)
/**
* dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
+ * Function: dc_enable_dmub_notifications
+ *
+ * @brief
+ * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
+ * notifications. All DMs shall switch to dc_is_dmub_outbox_supported.
+ * This API shall be removed after switching.
+ *
+ * @param
+ * [in] dc: dc structure
+ *
+ * @return
+ * True if DMUB FW supports outbox notifications, False otherwise
+ *****************************************************************************
+ */
+bool dc_enable_dmub_notifications(struct dc *dc)
+{
+ return dc_is_dmub_outbox_supported(dc);
+}
+
+/**
+ *****************************************************************************
+ * Function: dc_enable_dmub_outbox
+ *
+ * @brief
+ * Enables DMUB unsolicited notifications to x86 via outbox
+ *
+ * @param
+ * [in] dc: dc structure
+ *
+ * @return
+ * None
+ *****************************************************************************
+ */
+void dc_enable_dmub_outbox(struct dc *dc)
+{
+ struct dc_context *dc_ctx = dc->ctx;
+
+ dmub_enable_outbox_notification(dc_ctx->dmub_srv);
+}
+
+/**
+ *****************************************************************************
* Sets port index appropriately for legacy DDC
* @dc: dc structure
* @link_index: link index
@@ -3825,7 +3879,7 @@ uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
* [in] payload: aux payload
* [out] notify: set_config immediate reply
*
- * @return
+ * @return
* True if successful, False if failure
*****************************************************************************
*/
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index fcb021bf0c96..2957758a7abd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1443,8 +1443,11 @@ void dc_z10_restore(const struct dc *dc);
void dc_z10_save_init(struct dc *dc);
#endif
+bool dc_is_dmub_outbox_supported(struct dc *dc);
bool dc_enable_dmub_notifications(struct dc *dc);
+void dc_enable_dmub_outbox(struct dc *dc);
+
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
uint32_t link_index,
struct aux_payload *payload);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
index faad8555ddbb..fff1d07d865d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
@@ -22,20 +22,23 @@
* Authors: AMD
*/
-#include "dmub_outbox.h"
+#include "dc.h"
#include "dc_dmub_srv.h"
+#include "dmub_outbox.h"
#include "dmub/inc/dmub_cmd.h"
-/**
- * dmub_enable_outbox_notification - Sends inbox cmd to dmub to enable outbox1
- * messages with interrupt. Dmub sends outbox1
- * message and triggers outbox1 interrupt.
- * @dc: dc structure
+/*
+ * Function: dmub_enable_outbox_notification
+ *
+ * @brief
+ * Sends inbox cmd to dmub for enabling outbox notifications to x86.
+ *
+ * @param
+ * [in] dmub_srv: dmub_srv structure
*/
-void dmub_enable_outbox_notification(struct dc *dc)
+void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)
{
union dmub_rb_cmd cmd;
- struct dc_context *dc_ctx = dc->ctx;
memset(&cmd, 0x0, sizeof(cmd));
cmd.outbox1_enable.header.type = DMUB_CMD__OUTBOX1_ENABLE;
@@ -45,7 +48,7 @@ void dmub_enable_outbox_notification(struct dc *dc)
sizeof(cmd.outbox1_enable.header);
cmd.outbox1_enable.enable = true;
- dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
- dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
- dc_dmub_srv_wait_idle(dc_ctx->dmub_srv);
+ dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
+ dc_dmub_srv_cmd_execute(dmub_srv);
+ dc_dmub_srv_wait_idle(dmub_srv);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h
index 4e0aa0d1a2d5..58ceabb9d497 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h
@@ -26,8 +26,8 @@
#ifndef _DMUB_OUTBOX_H_
#define _DMUB_OUTBOX_H_
-#include "dc.h"
+struct dc_dmub_srv;
-void dmub_enable_outbox_notification(struct dc *dc);
+void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv);
#endif /* _DMUB_OUTBOX_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 915eecb40788..8dc1afc03961 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1500,10 +1500,6 @@ void dcn10_init_hw(struct dc *dc)
hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
}
- /* Enable outbox notification feature of dmub */
- if (dc->debug.enable_dmub_aux_for_legacy_ddc)
- dmub_enable_outbox_notification(dc);
-
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index b2cfd277b913..ef72d2b82d64 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -194,7 +194,7 @@ void dcn31_init_hw(struct dc *dc)
/* Enables outbox notifications for usb4 dpia */
if (dc->res_pool->usb4_dpia_count)
- dmub_enable_outbox_notification(dc);
+ dmub_enable_outbox_notification(dc->ctx->dmub_srv);
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 03/11] drm/amd/display: dsc mst re-compute pbn for changes on hub
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 01/11] drm/amd/display: reset lane settings after each PHY repeater LT Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 02/11] drm/amd/display: Fix for dmub outbox notification enable Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 04/11] drm/amd/display: make sure pipe power gating reach requested hw state Jasdeep Dhillon
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, Roman Li, Hersen Wu,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Hersen Wu <hersenwu@amd.com>
[why]
when unplug 1 dp from dsc mst hub, atomic_check new request
dc_state only include info for the unplug dp. this will not
trigger re-compute pbn for displays still connected to hub.
[how] all displays connected to dsc hub are available in
dc->current_state, by comparing dc->current_state and new
request from atomic_chceck, it will provide info of
displays connected to hub and do pbn re-compute.
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Hersen Wu <hersenwu@amd.com>
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 53 ++++++++++++++++---
1 file changed, 45 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 8e97d21bdf5c..914d59821c03 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -911,22 +911,31 @@ static bool is_dsc_need_re_compute(
struct dc_state *dc_state,
struct dc_link *dc_link)
{
- int i;
+ int i, j;
bool is_dsc_need_re_compute = false;
+ struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
+ int new_stream_on_link_num = 0;
+ struct amdgpu_dm_connector *aconnector;
+ struct dc_stream_state *stream;
+ const struct dc *dc = dc_link->dc;
- /* only check phy used by mst branch */
+ /* only check phy used by dsc mst branch */
if (dc_link->type != dc_connection_mst_branch)
return false;
+ if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
+ dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
+ return false;
+
+ for (i = 0; i < MAX_PIPES; i++)
+ stream_on_link[i] = NULL;
+
/* check if there is mode change in new request */
for (i = 0; i < dc_state->stream_count; i++) {
- struct amdgpu_dm_connector *aconnector;
- struct dc_stream_state *stream;
struct drm_crtc_state *new_crtc_state;
struct drm_connector_state *new_conn_state;
stream = dc_state->streams[i];
-
if (!stream)
continue;
@@ -938,8 +947,10 @@ static bool is_dsc_need_re_compute(
if (!aconnector)
continue;
- new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
+ stream_on_link[new_stream_on_link_num] = aconnector;
+ new_stream_on_link_num++;
+ new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
if (!new_conn_state)
continue;
@@ -950,7 +961,6 @@ static bool is_dsc_need_re_compute(
continue;
new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
-
if (!new_crtc_state)
continue;
@@ -960,7 +970,34 @@ static bool is_dsc_need_re_compute(
if (new_crtc_state->enable && new_crtc_state->active) {
if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
new_crtc_state->connectors_changed)
- is_dsc_need_re_compute = true;
+ return true;
+ }
+ }
+
+ /* check current_state if there stream on link but it is not in
+ * new request state
+ */
+ for (i = 0; i < dc->current_state->stream_count; i++) {
+ stream = dc->current_state->streams[i];
+ /* only check stream on the mst hub */
+ if (stream->link != dc_link)
+ continue;
+
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+ if (!aconnector)
+ continue;
+
+ for (j = 0; j < new_stream_on_link_num; j++) {
+ if (stream_on_link[j]) {
+ if (aconnector == stream_on_link[j])
+ break;
+ }
+ }
+
+ if (j == new_stream_on_link_num) {
+ /* not in new state */
+ is_dsc_need_re_compute = true;
+ break;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 04/11] drm/amd/display: make sure pipe power gating reach requested hw state
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (2 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 03/11] drm/amd/display: dsc mst re-compute pbn for changes on hub Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 05/11] drm/amd/display: enable z9 denial interface by default Jasdeep Dhillon
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Charlene Liu, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Jasdeep Dhillon, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Sung joon Kim,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Charlene Liu <Charlene.Liu@amd.com>
[why]
display mapping change will involved pipe power gating on and off.
when doing this too fase, sometimes usbc will have no display.
check HW status, it is still in pipe power gating.
[how]
insert polling HW status to make sure the required state reached.
also add dal registry key handling.
Reviewed-by: Sung joon Kim <Sungjoon.Kim@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 21 ++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index ef72d2b82d64..4be228680909 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -339,21 +339,31 @@ void dcn31_enable_power_gating_plane(
{
bool force_on = true; /* disable power gating */
- if (enable)
+ if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
force_on = false;
/* DCHUBP0/1/2/3/4/5 */
REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-
+ REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
/* DPP0/1/2/3/4/5 */
REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
+
+ force_on = true; /* disable power gating */
+ if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
+ force_on = false;
/* DCS0/1/2/3/4/5 */
REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+ REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
}
void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
@@ -419,12 +429,15 @@ void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool p
{
uint32_t power_gate = power_on ? 0 : 1;
uint32_t pwr_status = power_on ? 0 : 2;
-
+ uint32_t org_ip_request_cntl;
if (hws->ctx->dc->debug.disable_hubp_power_gate)
return;
if (REG(DOMAIN0_PG_CONFIG) == 0)
return;
+ REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+ if (org_ip_request_cntl == 0)
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
switch (hubp_inst) {
case 0:
@@ -447,6 +460,8 @@ void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool p
BREAK_TO_DEBUGGER();
break;
}
+ if (org_ip_request_cntl == 0)
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 05/11] drm/amd/display: enable z9 denial interface by default
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (3 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 04/11] drm/amd/display: make sure pipe power gating reach requested hw state Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 06/11] drm/amd/display: Add affected crtcs to atomic state for dsc mst unplug Jasdeep Dhillon
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Eric Yang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
Nicholas Kazlauskas, agustin.gutierrez, pavle.kotarac
From: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 007a7dc4f5be..5f5c21a2023e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1033,7 +1033,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.optimize_edp_link_rate = true,
.enable_sw_cntl_psr = true,
.apply_vendor_specific_lttpr_wa = true,
- .enable_z9_disable_interface = false
+ .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
};
static const struct dc_debug_options debug_defaults_diags = {
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 06/11] drm/amd/display: Add affected crtcs to atomic state for dsc mst unplug
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (4 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 05/11] drm/amd/display: enable z9 denial interface by default Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 07/11] drm/amd/display: [FW Promotion] Release 0.0.104.0 Jasdeep Dhillon
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, Roman Li, solomon.chiu,
Aurabindo.Pillai, Hersen Wu, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Roman Li <Roman.Li@amd.com>
[Why]
When display topology changed on DSC hub we add all crtcs with dsc support to
atomic state.
Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors"
However the original implementation may skip crtc if the topology change
caused by unplug.
That potentially could lead to no-lightup or corruption on DSC hub after
unplug event on one of the connectors.
[How]
Update add_affected_mst_dsc_crtcs() to use old connector state
if new connector state has no crtc (undergoes modeset due to unplug)
Fixes: ("drm/amd/display: Trigger modesets on MST DSC connectors")
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 10ca3fc6d91e..e26217e46c57 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10851,10 +10851,13 @@ static int dm_check_crtc_cursor(struct drm_atomic_state *state,
static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
struct drm_connector *connector;
- struct drm_connector_state *conn_state;
+ struct drm_connector_state *conn_state, *old_conn_state;
struct amdgpu_dm_connector *aconnector = NULL;
int i;
- for_each_new_connector_in_state(state, connector, conn_state, i) {
+ for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
+ if (!conn_state->crtc)
+ conn_state = old_conn_state;
+
if (conn_state->crtc != crtc)
continue;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 07/11] drm/amd/display: [FW Promotion] Release 0.0.104.0
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (5 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 06/11] drm/amd/display: Add affected crtcs to atomic state for dsc mst unplug Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 08/11] drm/amd/display: 3.2.173 Jasdeep Dhillon
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Anthony Koo, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Jasdeep Dhillon, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index c5cbbb0470ee..b01cb5493b76 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5189adbf
+#define DMUB_FW_VERSION_GIT_HASH 0x1422ef84
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 103
+#define DMUB_FW_VERSION_REVISION 104
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 08/11] drm/amd/display: 3.2.173
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (6 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 07/11] drm/amd/display: [FW Promotion] Release 0.0.104.0 Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 09/11] drm/amd/display: add dsc mst stream pbn log for debug Jasdeep Dhillon
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Aric Cyr, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Aric Cyr <aric.cyr@amd.com>
This version brings along the following fixes:
-Fixes bugs for dsc mst hub
-Enables 29 denial itnerface by default
-Fixes dmub outbox notificatoin
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2957758a7abd..e2b3ad70635b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.172"
+#define DC_VER "3.2.173"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 09/11] drm/amd/display: add dsc mst stream pbn log for debug
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (7 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 08/11] drm/amd/display: 3.2.173 Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 10/11] drm/amd/display: Add dsc pre-validation in atomic check Jasdeep Dhillon
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, roman.li, Hersen Wu,
solomon.chiu, Jerry Zuo, Aurabindo.Pillai, Hersen Wu, wayne.lin,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Hersen Wu <hersenwu@amd.com>
[why]
payload and slot number of display on dsc mst hub will be
adjusted when there is change on any display on dsc hub.
to monitor dsc enable/disable, pbn change, we need add log.
[How]
add mst_pbn to dc_dsc_config of dc_crtc_timing.
add dsc, pbn, display name within dc_core_enable_stream,
dc_core_disable_stream, dc_stream_log
Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 15 ++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 +++++++++++++++++++
.../gpu/drm/amd/display/dc/core/dc_stream.c | 16 +++++++++++++++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
4 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 914d59821c03..52ce5cc6462f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -599,6 +599,21 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
} else {
params[i].timing->flags.DSC = 0;
}
+ params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (params[i].sink) {
+ if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
+ params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
+ DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
+ params[i].sink->edid_caps.display_name);
+ }
+
+ DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
+ params[i].timing->flags.DSC,
+ params[i].timing->dsc_cfg.bits_per_pixel,
+ vars[i + k].pbn);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b1718600fa02..48858e31b092 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4082,6 +4082,15 @@ void core_link_enable_stream(
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+ if (pipe_ctx->stream->sink) {
+ if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
+ pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
+ DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
+ pipe_ctx->stream->sink->edid_caps.display_name,
+ pipe_ctx->stream->signal);
+ }
+ }
+
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
@@ -4303,6 +4312,17 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
if (is_dp_128b_132b_signal(pipe_ctx))
vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+
+ if (pipe_ctx->stream->sink) {
+ if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
+ pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
+ DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
+ pipe_ctx->stream->sink->edid_caps.display_name,
+ pipe_ctx->stream->signal);
+ }
+ }
+
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 57cf4cb82370..263f9891ecbc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -737,5 +737,21 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
DC_LOG_DC(
"\tlink: %d\n",
stream->link->link_index);
+
+ DC_LOG_DC(
+ "\tdsc: %d, mst_pbn: %d\n",
+ stream->timing.flags.DSC,
+ stream->timing.dsc_cfg.mst_pbn);
+
+ if (stream->sink) {
+ if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
+ stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
+
+ DC_LOG_DC(
+ "\tdispname: %s signal: %x\n",
+ stream->sink->edid_caps.display_name,
+ stream->signal);
+ }
+ }
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index eac34f591a3f..c964f598755a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -745,6 +745,7 @@ struct dc_dsc_config {
bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
#endif
bool is_dp; /* indicate if DSC is applied based on DP's capability */
+ uint32_t mst_pbn; /* pbn of display on dsc mst hub */
};
struct dc_crtc_timing {
uint32_t h_total;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 10/11] drm/amd/display: Add dsc pre-validation in atomic check
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (8 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 09/11] drm/amd/display: add dsc mst stream pbn log for debug Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-11 21:51 ` [PATCH 11/11] drm/amd/display: extend dcn201 support Jasdeep Dhillon
2022-02-14 21:12 ` [PATCH 00/11] DC Patches Feburary 14, 2022 Wheeler, Daniel
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Jasdeep Dhillon, Rodrigo.Siqueira, Roman Li, solomon.chiu,
Aurabindo.Pillai, Hersen Wu, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Roman Li <Roman.Li@amd.com>
[Why]
The previous change:
"Add affected crtcs to atomic state for dsc mst unplug"
forces modeset on all added crctc regardless whether timing changed or not.
Per our implementation of dsc we need modeset only if timing changed.
Otherwise dsc can be programmed incorrectly leading to dsc engine hang.
[How]
During atomic_check pre-compute dsc params.
Only set mode_changed if timing is changed.
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 13 ++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 189 ++++++++++++++++++
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
5 files changed, 213 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e26217e46c57..e69c3415801e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2406,7 +2406,7 @@ static int dm_suspend(void *handle)
return 0;
}
-static struct amdgpu_dm_connector *
+struct amdgpu_dm_connector *
amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
struct drm_crtc *crtc)
{
@@ -3723,7 +3723,7 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev)
*
* This should only be called during atomic check.
*/
-static int dm_atomic_get_state(struct drm_atomic_state *state,
+int dm_atomic_get_state(struct drm_atomic_state *state,
struct dm_atomic_state **dm_state)
{
struct drm_device *dev = state->dev;
@@ -6349,7 +6349,7 @@ static bool is_freesync_video_mode(const struct drm_display_mode *mode,
return true;
}
-static struct dc_stream_state *
+struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
const struct dm_connector_state *dm_state,
@@ -7002,7 +7002,7 @@ static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
create_eml_sink(aconnector);
}
-static struct dc_stream_state *
+struct dc_stream_state *
create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
const struct dm_connector_state *dm_state,
@@ -10176,7 +10176,7 @@ static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
}
-static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
+int dm_update_crtc_state(struct amdgpu_display_manager *dm,
struct drm_atomic_state *state,
struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state,
@@ -10964,6 +10964,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
}
}
+ pre_validate_dsc(state, &dm_state, vars);
}
#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index e35977fda5c1..03d457f8a5f1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -737,4 +737,17 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux,
bool check_seamless_boot_capability(struct amdgpu_device *adev);
+struct dc_stream_state *create_validate_stream_for_sink(
+ struct amdgpu_dm_connector *aconnector,
+ const struct drm_display_mode *drm_mode,
+ const struct dm_connector_state *dm_state,
+ const struct dc_stream_state *old_stream);
+
+int dm_atomic_get_state(
+ struct drm_atomic_state *state,
+ struct dm_atomic_state **dm_state);
+
+struct amdgpu_dm_connector *amdgpu_dm_find_first_crtc_matching_connector(
+ struct drm_atomic_state *state,
+ struct drm_crtc *crtc);
#endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 52ce5cc6462f..d881b094ce28 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -47,6 +47,9 @@
#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dc/dcn20/dcn20_resource.h"
+bool is_timing_changed(struct dc_stream_state *cur_stream,
+ struct dc_stream_state *new_stream);
+
#endif
static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
@@ -1079,5 +1082,191 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
return true;
}
+static bool pre_compute_mst_dsc_configs_for_state(
+ struct drm_atomic_state *state,
+ struct dc_state *dc_state,
+ struct dsc_mst_fairness_vars *vars)
+{
+ int i, j;
+ struct dc_stream_state *stream;
+ bool computed_streams[MAX_PIPES];
+ struct amdgpu_dm_connector *aconnector;
+ int link_vars_start_index = 0;
+
+ for (i = 0; i < dc_state->stream_count; i++)
+ computed_streams[i] = false;
+
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
+ continue;
+
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+ if (!aconnector || !aconnector->dc_sink)
+ continue;
+
+ if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
+ continue;
+
+ if (computed_streams[i])
+ continue;
+
+ if (!is_dsc_need_re_compute(state, dc_state, stream->link))
+ continue;
+
+ mutex_lock(&aconnector->mst_mgr.lock);
+ if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link,
+ vars, &link_vars_start_index)) {
+ mutex_unlock(&aconnector->mst_mgr.lock);
+ return false;
+ }
+ mutex_unlock(&aconnector->mst_mgr.lock);
+
+ for (j = 0; j < dc_state->stream_count; j++) {
+ if (dc_state->streams[j]->link == stream->link)
+ computed_streams[j] = true;
+ }
+ }
+
+ return true;
+}
+
+static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
+ struct dc_stream_state *stream)
+{
+ int i;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_state, *old_state;
+
+ for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
+ struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
+ if (dm_state->stream == stream)
+ return i;
+ }
+ return -1;
+}
+static bool is_link_to_dschub(struct dc_link *dc_link)
+{
+ union dpcd_dsc_basic_capabilities *dsc_caps =
+ &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
+
+ /* only check phy used by dsc mst branch */
+ if (dc_link->type != dc_connection_mst_branch)
+ return false;
+
+ if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
+ dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
+ return false;
+ return true;
+}
+
+static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
+{
+ uint32_t i;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+ bool ret = false;
+
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+ if (amdgpu_dm_find_first_crtc_matching_connector(state, crtc) == NULL) {
+ ret = false;
+ break;
+ }
+ if (dm_crtc_state->stream && dm_crtc_state->stream->link)
+ if (is_link_to_dschub(dm_crtc_state->stream->link))
+ ret = true;
+ }
+ return ret;
+}
+
+void pre_validate_dsc(struct drm_atomic_state *state,
+ struct dm_atomic_state **dm_state_ptr,
+ struct dsc_mst_fairness_vars *vars)
+{
+ uint32_t i;
+ struct dm_atomic_state *dm_state;
+ struct dc_state *local_dc_state = NULL;
+
+ if (!is_dsc_precompute_needed(state)) {
+ DRM_DEBUG_DRIVER("DSC precompute is not needed.\n");
+ return;
+ }
+ if (dm_atomic_get_state(state, dm_state_ptr)) {
+ DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
+ return;
+ }
+ dm_state = *dm_state_ptr;
+
+ /*
+ * create local vailable for dc_state. copy content of streams of dm_state->context
+ * to local variable. make sure stream pointer of local variable not the same as stream
+ * from dm_state->context.
+ */
+
+ local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
+ if (!local_dc_state)
+ return;
+
+ for (i = 0; i < local_dc_state->stream_count; i++) {
+ struct dc_stream_state *stream = dm_state->context->streams[i];
+ int ind = find_crtc_index_in_state_by_stream(state, stream);
+
+ if (ind >= 0) {
+ struct amdgpu_dm_connector *aconnector;
+ struct drm_connector_state *drm_new_conn_state;
+ struct dm_connector_state *dm_new_conn_state;
+ struct dm_crtc_state *dm_old_crtc_state;
+
+ aconnector = amdgpu_dm_find_first_crtc_matching_connector(state,
+ state->crtcs[ind].ptr);
+ drm_new_conn_state = drm_atomic_get_new_connector_state(state,
+ &aconnector->base);
+ dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
+ dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
+
+ local_dc_state->streams[i] = create_validate_stream_for_sink(aconnector,
+ &state->crtcs[ind].new_state->mode,
+ dm_new_conn_state,
+ dm_old_crtc_state->stream);
+ }
+ }
+
+ if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) {
+ DRM_DEBUG_DRIVER("pre_compute_mst_dsc_configs_for_state() failed\n");
+ goto clean_exit;
+ }
+
+
+ /*
+ * compare local_streams -> timing with dm_state->context,
+ * if the same set crtc_state->mode-change = 0;
+ */
+ for (i = 0; i < local_dc_state->stream_count; i++) {
+ struct dc_stream_state *stream = dm_state->context->streams[i];
+
+ if (local_dc_state->streams[i] &&
+ is_timing_changed(stream, local_dc_state->streams[i])) {
+ DRM_DEBUG_DRIVER("crtc[%d] needs mode_changed\n", i);
+ } else {
+ int ind = find_crtc_index_in_state_by_stream(state, stream);
+
+ if (ind >= 0)
+ state->crtcs[ind].new_state->mode_changed = 0;
+ }
+ }
+clean_exit:
+ for (i = 0; i < local_dc_state->stream_count; i++) {
+ struct dc_stream_state *stream = dm_state->context->streams[i];
+
+ if (local_dc_state->streams[i] != stream)
+ dc_stream_release(local_dc_state->streams[i]);
+ }
+
+ kfree(local_dc_state);
+}
#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 5da28ca03372..c561e0d872d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -60,6 +60,10 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
struct dsc_mst_fairness_vars *vars);
bool needs_dsc_aux_workaround(struct dc_link *link);
+
+void pre_validate_dsc(struct drm_atomic_state *state,
+ struct dm_atomic_state **dm_state_ptr,
+ struct dsc_mst_fairness_vars *vars);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b36bae4b5bc9..23e113dc0790 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1614,7 +1614,7 @@ bool dc_add_all_planes_for_stream(
return add_all_planes_for_stream(dc, stream, &set, 1, context);
}
-static bool is_timing_changed(struct dc_stream_state *cur_stream,
+bool is_timing_changed(struct dc_stream_state *cur_stream,
struct dc_stream_state *new_stream)
{
if (cur_stream == NULL)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 11/11] drm/amd/display: extend dcn201 support
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (9 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 10/11] drm/amd/display: Add dsc pre-validation in atomic check Jasdeep Dhillon
@ 2022-02-11 21:51 ` Jasdeep Dhillon
2022-02-14 21:12 ` [PATCH 00/11] DC Patches Feburary 14, 2022 Wheeler, Daniel
11 siblings, 0 replies; 13+ messages in thread
From: Jasdeep Dhillon @ 2022-02-11 21:51 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Oliver Logush, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Oliver Logush <ollogush@amd.com>
Signed-off-by: Oliver Logush <ollogush@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 23e113dc0790..e363859f34d3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -135,7 +135,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
case FAMILY_NV:
dc_version = DCN_VERSION_2_0;
- if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
+ if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_1400) {
dc_version = DCN_VERSION_2_01;
break;
}
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index e4a2dfacab4c..a8dcd6d439c6 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -212,6 +212,7 @@ enum {
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
#endif
#define DEVICE_ID_NV_13FE 0x13FE // CYAN_SKILLFISH
+#define DEVICE_ID_NV_1400 0x1400
#define FAMILY_VGH 144
#define DEVICE_ID_VGH_163F 0x163F
#define VANGOGH_A0 0x01
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* RE: [PATCH 00/11] DC Patches Feburary 14, 2022
2022-02-11 21:51 [PATCH 00/11] DC Patches Feburary 14, 2022 Jasdeep Dhillon
` (10 preceding siblings ...)
2022-02-11 21:51 ` [PATCH 11/11] drm/amd/display: extend dcn201 support Jasdeep Dhillon
@ 2022-02-14 21:12 ` Wheeler, Daniel
11 siblings, 0 replies; 13+ messages in thread
From: Wheeler, Daniel @ 2022-02-14 21:12 UTC (permalink / raw)
To: Dhillon, Jasdeep, amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon), Li, Sun peng (Leo), Wentland, Harry,
Zhuo, Qingqing (Lillian), Siqueira, Rodrigo, Li, Roman,
Lakha, Bhawanpreet, Chiu, Solomon, Pillai, Aurabindo, Lin, Wayne,
Dhillon, Jasdeep, Gutierrez, Agustin, Kotarac, Pavle
[AMD Official Use Only]
Hi all,
This week this patchset was tested on the following systems:
Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Also tested DSC via USB-C to DP DSC Hub with 3x 4k 60hz on Ryzen 9 5900h and Ryzen 5 4500u.
Tested on Ubuntu 20.04.3 with Kernel Version 5.13
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Jasdeep Dhillon
Sent: February 11, 2022 4:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Dhillon, Jasdeep <Jasdeep.Dhillon@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: [PATCH 00/11] DC Patches Feburary 14, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight:
-Fixes bugs for dsc mst hub
-Enables Z9 denial interface by default
-Fixes dmub outbox notification
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.104.0
Aric Cyr (1):
drm/amd/display: 3.2.173
Charlene Liu (1):
drm/amd/display: make sure pipe power gating reach requested hw state
Eric Yang (1):
drm/amd/display: enable z9 denial interface by default
Hersen Wu (2):
drm/amd/display: dsc mst re-compute pbn for changes on hub
drm/amd/display: add dsc mst stream pbn log for debug
Meenakshikumar Somasundaram (1):
drm/amd/display: Fix for dmub outbox notification enable
Oliver Logush (1):
drm/amd/display: extend dcn201 support
Roman Li (2):
drm/amd/display: Add affected crtcs to atomic state for dsc mst unplug
drm/amd/display: Add dsc pre-validation in atomic check
Sung Joon Kim (1):
drm/amd/display: reset lane settings after each PHY repeater LT
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 13 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 257 +++++++++++++++++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 66 ++++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 ++ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 16 ++
drivers/gpu/drm/amd/display/dc/dc.h | 5 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
.../gpu/drm/amd/display/dc/dce/dmub_outbox.c | 25 +-
.../gpu/drm/amd/display/dc/dce/dmub_outbox.h | 4 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 -
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 23 +-
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +-
.../gpu/drm/amd/display/include/dal_asic_id.h | 1 +
18 files changed, 429 insertions(+), 53 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 13+ messages in thread