From: Shawn Guo <shawnguo@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support
Date: Mon, 21 Feb 2022 16:31:49 +0800 [thread overview]
Message-ID: <20220221083149.GS2249@dragon> (raw)
In-Reply-To: <1645425237-4071-1-git-send-email-hongxing.zhu@nxp.com>
On Mon, Feb 21, 2022 at 02:33:56PM +0800, Richard Zhu wrote:
> In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
> is powered up by vgen3 and used as the PCIe reference clock source by
> the endpoint device.
>
> If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
> has to be in bypass mode, and ENET clocks would be messed up.
>
> To keep things simple, let RC use the internal PLL as reference clock
> and set vgen3 always on to enable the external oscillator for endpoint
> device on i.MX6QP sabresd board.
>
> NOTE: This reference clock setup is used to pass the GEN2 TX compliance
> tests, and isn't recommended as a setup in the end-user design.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Applied, thanks!
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support
Date: Mon, 21 Feb 2022 16:31:49 +0800 [thread overview]
Message-ID: <20220221083149.GS2249@dragon> (raw)
In-Reply-To: <1645425237-4071-1-git-send-email-hongxing.zhu@nxp.com>
On Mon, Feb 21, 2022 at 02:33:56PM +0800, Richard Zhu wrote:
> In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
> is powered up by vgen3 and used as the PCIe reference clock source by
> the endpoint device.
>
> If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
> has to be in bypass mode, and ENET clocks would be messed up.
>
> To keep things simple, let RC use the internal PLL as reference clock
> and set vgen3 always on to enable the external oscillator for endpoint
> device on i.MX6QP sabresd board.
>
> NOTE: This reference clock setup is used to pass the GEN2 TX compliance
> tests, and isn't recommended as a setup in the end-user design.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Applied, thanks!
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next prev parent reply other threads:[~2022-02-21 8:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 6:33 [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support Richard Zhu
2022-02-21 6:33 ` Richard Zhu
2022-02-21 6:33 ` [PATCH v4 2/2] PCI: imx6: Enable i.MX6QP PCIe power management support Richard Zhu
2022-02-21 6:33 ` Richard Zhu
2022-02-21 8:31 ` Shawn Guo [this message]
2022-02-21 8:31 ` [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support Shawn Guo
2022-03-07 11:09 ` (subset) " Lorenzo Pieralisi
2022-03-07 11:09 ` Lorenzo Pieralisi
2022-03-08 1:19 ` Hongxing Zhu
2022-03-08 1:19 ` Hongxing Zhu
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