* [net 1/5] net/mlx5: Fix size field in bufferx_reg struct
2022-03-09 20:15 [pull request][net 0/5] mlx5 fixes 2022-03-09 Saeed Mahameed
@ 2022-03-09 20:15 ` Saeed Mahameed
2022-03-10 22:40 ` patchwork-bot+netdevbpf
2022-03-09 20:15 ` [net 2/5] net/mlx5: Fix a race on command flush flow Saeed Mahameed
` (3 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Saeed Mahameed @ 2022-03-09 20:15 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Mohammad Kabat, Moshe Shemesh, Saeed Mahameed
From: Mohammad Kabat <mohammadkab@nvidia.com>
According to HW spec the field "size" should be 16 bits
in bufferx register.
Fixes: e281682bf294 ("net/mlx5_core: HW data structs/types definitions cleanup")
Signed-off-by: Mohammad Kabat <mohammadkab@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
include/linux/mlx5/mlx5_ifc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 598ac3bcc901..5743f5b3414b 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -9900,8 +9900,8 @@ struct mlx5_ifc_bufferx_reg_bits {
u8 reserved_at_0[0x6];
u8 lossy[0x1];
u8 epsb[0x1];
- u8 reserved_at_8[0xc];
- u8 size[0xc];
+ u8 reserved_at_8[0x8];
+ u8 size[0x10];
u8 xoff_threshold[0x10];
u8 xon_threshold[0x10];
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [net 1/5] net/mlx5: Fix size field in bufferx_reg struct
2022-03-09 20:15 ` [net 1/5] net/mlx5: Fix size field in bufferx_reg struct Saeed Mahameed
@ 2022-03-10 22:40 ` patchwork-bot+netdevbpf
0 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+netdevbpf @ 2022-03-10 22:40 UTC (permalink / raw)
To: Saeed Mahameed; +Cc: davem, kuba, netdev, mohammadkab, moshe, saeedm
Hello:
This series was applied to netdev/net.git (master)
by Saeed Mahameed <saeedm@nvidia.com>:
On Wed, 9 Mar 2022 12:15:13 -0800 you wrote:
> From: Mohammad Kabat <mohammadkab@nvidia.com>
>
> According to HW spec the field "size" should be 16 bits
> in bufferx register.
>
> Fixes: e281682bf294 ("net/mlx5_core: HW data structs/types definitions cleanup")
> Signed-off-by: Mohammad Kabat <mohammadkab@nvidia.com>
> Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
>
> [...]
Here is the summary with links:
- [net,1/5] net/mlx5: Fix size field in bufferx_reg struct
https://git.kernel.org/netdev/net/c/ac77998b7ac3
- [net,2/5] net/mlx5: Fix a race on command flush flow
https://git.kernel.org/netdev/net/c/063bd3555954
- [net,3/5] net/mlx5: Fix offloading with ESWITCH_IPV4_TTL_MODIFY_ENABLE
https://git.kernel.org/netdev/net/c/39bab83b119f
- [net,4/5] net/mlx5e: Lag, Only handle events from highest priority multipath entry
https://git.kernel.org/netdev/net/c/ad11c4f1d8fd
- [net,5/5] net/mlx5e: SHAMPO, reduce TIR indication
https://git.kernel.org/netdev/net/c/99a2b9be077a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread
* [net 2/5] net/mlx5: Fix a race on command flush flow
2022-03-09 20:15 [pull request][net 0/5] mlx5 fixes 2022-03-09 Saeed Mahameed
2022-03-09 20:15 ` [net 1/5] net/mlx5: Fix size field in bufferx_reg struct Saeed Mahameed
@ 2022-03-09 20:15 ` Saeed Mahameed
2022-03-09 20:15 ` [net 3/5] net/mlx5: Fix offloading with ESWITCH_IPV4_TTL_MODIFY_ENABLE Saeed Mahameed
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2022-03-09 20:15 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Moshe Shemesh, Eran Ben Elisha, Saeed Mahameed
From: Moshe Shemesh <moshe@nvidia.com>
Fix a refcount use after free warning due to a race on command entry.
Such race occurs when one of the commands releases its last refcount and
frees its index and entry while another process running command flush
flow takes refcount to this command entry. The process which handles
commands flush may see this command as needed to be flushed if the other
process released its refcount but didn't release the index yet. Fix it
by adding the needed spin lock.
It fixes the following warning trace:
refcount_t: addition on 0; use-after-free.
WARNING: CPU: 11 PID: 540311 at lib/refcount.c:25 refcount_warn_saturate+0x80/0xe0
...
RIP: 0010:refcount_warn_saturate+0x80/0xe0
...
Call Trace:
<TASK>
mlx5_cmd_trigger_completions+0x293/0x340 [mlx5_core]
mlx5_cmd_flush+0x3a/0xf0 [mlx5_core]
enter_error_state+0x44/0x80 [mlx5_core]
mlx5_fw_fatal_reporter_err_work+0x37/0xe0 [mlx5_core]
process_one_work+0x1be/0x390
worker_thread+0x4d/0x3d0
? rescuer_thread+0x350/0x350
kthread+0x141/0x160
? set_kthread_struct+0x40/0x40
ret_from_fork+0x1f/0x30
</TASK>
Fixes: 50b2412b7e78 ("net/mlx5: Avoid possible free of command entry while timeout comp handler")
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Eran Ben Elisha <eranbe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
index 17fe05809653..3eacd8739929 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
@@ -131,11 +131,8 @@ static int cmd_alloc_index(struct mlx5_cmd *cmd)
static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
{
- unsigned long flags;
-
- spin_lock_irqsave(&cmd->alloc_lock, flags);
+ lockdep_assert_held(&cmd->alloc_lock);
set_bit(idx, &cmd->bitmask);
- spin_unlock_irqrestore(&cmd->alloc_lock, flags);
}
static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
@@ -145,17 +142,21 @@ static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
{
+ struct mlx5_cmd *cmd = ent->cmd;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cmd->alloc_lock, flags);
if (!refcount_dec_and_test(&ent->refcnt))
- return;
+ goto out;
if (ent->idx >= 0) {
- struct mlx5_cmd *cmd = ent->cmd;
-
cmd_free_index(cmd, ent->idx);
up(ent->page_queue ? &cmd->pages_sem : &cmd->sem);
}
cmd_free_ent(ent);
+out:
+ spin_unlock_irqrestore(&cmd->alloc_lock, flags);
}
static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [net 3/5] net/mlx5: Fix offloading with ESWITCH_IPV4_TTL_MODIFY_ENABLE
2022-03-09 20:15 [pull request][net 0/5] mlx5 fixes 2022-03-09 Saeed Mahameed
2022-03-09 20:15 ` [net 1/5] net/mlx5: Fix size field in bufferx_reg struct Saeed Mahameed
2022-03-09 20:15 ` [net 2/5] net/mlx5: Fix a race on command flush flow Saeed Mahameed
@ 2022-03-09 20:15 ` Saeed Mahameed
2022-03-09 20:15 ` [net 4/5] net/mlx5e: Lag, Only handle events from highest priority multipath entry Saeed Mahameed
2022-03-09 20:15 ` [net 5/5] net/mlx5e: SHAMPO, reduce TIR indication Saeed Mahameed
4 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2022-03-09 20:15 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Dima Chumak, Roi Dayan, Saeed Mahameed
From: Dima Chumak <dchumak@nvidia.com>
Only prio 1 is supported for nic mode when there is no ignore flow level
support in firmware. But for switchdev mode, which supports fixed number
of statically pre-allocated prios, this restriction is not relevant so
it can be relaxed.
Fixes: d671e109bd85 ("net/mlx5: Fix tc max supported prio for nic mode")
Signed-off-by: Dima Chumak <dchumak@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c
index 1e8ec4f236b2..df58cba37930 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c
@@ -121,9 +121,6 @@ u32 mlx5_chains_get_nf_ft_chain(struct mlx5_fs_chains *chains)
u32 mlx5_chains_get_prio_range(struct mlx5_fs_chains *chains)
{
- if (!mlx5_chains_prios_supported(chains))
- return 1;
-
if (mlx5_chains_ignore_flow_level_supported(chains))
return UINT_MAX;
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [net 4/5] net/mlx5e: Lag, Only handle events from highest priority multipath entry
2022-03-09 20:15 [pull request][net 0/5] mlx5 fixes 2022-03-09 Saeed Mahameed
` (2 preceding siblings ...)
2022-03-09 20:15 ` [net 3/5] net/mlx5: Fix offloading with ESWITCH_IPV4_TTL_MODIFY_ENABLE Saeed Mahameed
@ 2022-03-09 20:15 ` Saeed Mahameed
2022-03-09 20:15 ` [net 5/5] net/mlx5e: SHAMPO, reduce TIR indication Saeed Mahameed
4 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2022-03-09 20:15 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Roi Dayan, Maor Dickman, Saeed Mahameed
From: Roi Dayan <roid@nvidia.com>
There could be multiple multipath entries but changing the port affinity
for each one doesn't make much sense and there should be a default one.
So only track the entry with lowest priority value.
The commit doesn't affect existing users with a single entry.
Fixes: 544fe7c2e654 ("net/mlx5e: Activate HW multipath and handle port affinity based on FIB events")
Signed-off-by: Roi Dayan <roid@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c
index 1ca01a5b6cdd..626aa60b6099 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c
@@ -126,6 +126,10 @@ static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev,
return;
}
+ /* Handle multipath entry with lower priority value */
+ if (mp->mfi && mp->mfi != fi && fi->fib_priority >= mp->mfi->fib_priority)
+ return;
+
/* Handle add/replace event */
nhs = fib_info_num_path(fi);
if (nhs == 1) {
@@ -135,12 +139,13 @@ static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev,
int i = mlx5_lag_dev_get_netdev_idx(ldev, nh_dev);
if (i < 0)
- i = MLX5_LAG_NORMAL_AFFINITY;
- else
- ++i;
+ return;
+ i++;
mlx5_lag_set_port_affinity(ldev, i);
}
+
+ mp->mfi = fi;
return;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [net 5/5] net/mlx5e: SHAMPO, reduce TIR indication
2022-03-09 20:15 [pull request][net 0/5] mlx5 fixes 2022-03-09 Saeed Mahameed
` (3 preceding siblings ...)
2022-03-09 20:15 ` [net 4/5] net/mlx5e: Lag, Only handle events from highest priority multipath entry Saeed Mahameed
@ 2022-03-09 20:15 ` Saeed Mahameed
4 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2022-03-09 20:15 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski; +Cc: netdev, Ben Ben-Ishay, Saeed Mahameed
From: Ben Ben-Ishay <benishay@nvidia.com>
SHAMPO is an RQ / WQ feature, an indication was added to the TIR in the
first place to enforce suitability between connected TIR and RQ, this
enforcement does not exist in current the Firmware implementation and was
redundant in the first place.
Fixes: 83439f3c37aa ("net/mlx5e: Add HW-GRO offload")
Signed-off-by: Ben Ben-Ishay <benishay@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/en/tir.c | 3 ---
drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 3 +--
include/linux/mlx5/mlx5_ifc.h | 1 -
3 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c
index da169b816665..d4239e3b3c88 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c
@@ -88,9 +88,6 @@ void mlx5e_tir_builder_build_packet_merge(struct mlx5e_tir_builder *builder,
(MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - rough_max_l2_l3_hdr_sz) >> 8);
MLX5_SET(tirc, tirc, lro_timeout_period_usecs, pkt_merge_param->timeout);
break;
- case MLX5E_PACKET_MERGE_SHAMPO:
- MLX5_SET(tirc, tirc, packet_merge_mask, MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO);
- break;
default:
break;
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index bf80fb612449..3667f5ef5990 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -3616,8 +3616,7 @@ static int set_feature_hw_gro(struct net_device *netdev, bool enable)
goto out;
}
- err = mlx5e_safe_switch_params(priv, &new_params,
- mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
+ err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
out:
mutex_unlock(&priv->state_lock);
return err;
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 5743f5b3414b..49a48d7709ac 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -3434,7 +3434,6 @@ enum {
enum {
MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
- MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2),
};
enum {
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread