From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu
Cc: kernel-team@android.com, Andre Przywara <andre.przywara@arm.com>
Subject: [PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
Date: Mon, 14 Mar 2022 16:40:41 +0000 [thread overview]
Message-ID: <20220314164044.772709-2-maz@kernel.org> (raw)
In-Reply-To: <20220314164044.772709-1-maz@kernel.org>
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 12d91f0dedf9..aeb8ced53880 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -127,6 +127,8 @@
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+#define GICR_CTLR_IR (1UL << 1)
+#define GICR_CTLR_CES (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
--
2.34.1
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
kernel-team@android.com
Subject: [PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
Date: Mon, 14 Mar 2022 16:40:41 +0000 [thread overview]
Message-ID: <20220314164044.772709-2-maz@kernel.org> (raw)
In-Reply-To: <20220314164044.772709-1-maz@kernel.org>
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 12d91f0dedf9..aeb8ced53880 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -127,6 +127,8 @@
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+#define GICR_CTLR_IR (1UL << 1)
+#define GICR_CTLR_CES (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
kernel-team@android.com
Subject: [PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
Date: Mon, 14 Mar 2022 16:40:41 +0000 [thread overview]
Message-ID: <20220314164044.772709-2-maz@kernel.org> (raw)
In-Reply-To: <20220314164044.772709-1-maz@kernel.org>
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 12d91f0dedf9..aeb8ced53880 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -127,6 +127,8 @@
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+#define GICR_CTLR_IR (1UL << 1)
+#define GICR_CTLR_CES (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
--
2.34.1
next prev parent reply other threads:[~2022-03-14 16:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 16:40 [PATCH 0/4] KVM: arm64: vgic-v3: MMIO-based LPI invalidation and co Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier [this message]
2022-03-14 16:40 ` [PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Marc Zyngier
2022-03-14 16:40 ` [PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Marc Zyngier
2022-03-15 23:16 ` Oliver Upton
2022-03-15 23:16 ` Oliver Upton
2022-03-15 23:16 ` Oliver Upton
2022-03-16 9:29 ` Marc Zyngier
2022-03-16 9:29 ` Marc Zyngier
2022-03-16 9:29 ` Marc Zyngier
2022-03-14 16:40 ` [PATCH 2/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-16 5:26 ` Oliver Upton
2022-03-16 5:26 ` Oliver Upton
2022-03-16 5:26 ` Oliver Upton
2022-03-16 9:31 ` Marc Zyngier
2022-03-16 9:31 ` Marc Zyngier
2022-03-16 9:31 ` Marc Zyngier
2022-03-14 16:40 ` [PATCH 3/4] KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-14 16:40 ` Marc Zyngier
2022-03-16 5:39 ` Oliver Upton
2022-03-16 5:39 ` Oliver Upton
2022-03-16 5:39 ` Oliver Upton
2022-03-14 16:40 ` [PATCH 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} as a new GICD_IIDR revision Marc Zyngier
2022-03-14 16:40 ` [PATCH 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR,CES} " Marc Zyngier
2022-03-14 16:40 ` [PATCH 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} " Marc Zyngier
2022-03-15 23:13 ` Oliver Upton
2022-03-15 23:13 ` Oliver Upton
2022-03-15 23:13 ` Oliver Upton
2022-03-16 9:27 ` Marc Zyngier
2022-03-16 9:27 ` Marc Zyngier
2022-03-16 9:27 ` Marc Zyngier
2022-03-16 15:01 ` Marc Zyngier
2022-03-16 15:01 ` Marc Zyngier
2022-03-16 15:01 ` Marc Zyngier
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