* [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+
@ 2022-02-24 16:50 Ville Syrjala
2022-02-24 16:51 ` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming Ville Syrjala
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Ville Syrjala @ 2022-02-24 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
As we did with plane updates we can split the color management
updates to noarm+arm pair. The CSC matrix coefficients can all
be written in the noarm hook, with just the PIPE_CSC_mode (the
arming register) left behind in the arm hook.
Also make the scaler/pfit completely lockless as that too
adds overhead into the vblank evasion critical section.
Ville Syrjälä (4):
drm/i915: Remove locks around skl+ scaler programming
drm/i915: Make ilk+ pfit regiser unlocked
drm/i915: Split color_commit() into noarm+arm pair
drm/i915: Split pipe+output CSC programming to noarm+arm pair
drivers/gpu/drm/i915/display/intel_color.c | 95 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_color.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 40 +++++----
drivers/gpu/drm/i915/display/skl_scaler.c | 10 ---
4 files changed, 88 insertions(+), 60 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
@ 2022-02-24 16:51 ` Ville Syrjala
2022-03-29 9:28 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked Ville Syrjala
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2022-02-24 16:51 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the skl+ scaler registers are suitably confined to their own
cachelines so we don't need the uncore.lock to globally serialize
access to these registers. We actually already dropped some of this
in commit 14ad15296d1f ("drm/i915: Make skl+ universal plane
registers unlocked") as the plane scaler enabling/reconfiguration
became lockless. So let's complete that and remove the rest of
the locks from the scaler programming as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c2e94118566b..ac67e9fbb713 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -412,7 +412,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
int x = dst->x1;
int y = dst->y1;
int hscale, vscale;
- unsigned long irqflags;
int id;
u32 ps_ctrl;
@@ -434,8 +433,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
crtc_state->hw.scaling_filter);
@@ -449,8 +446,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
x << 16 | y);
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
width << 16 | height);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
void
@@ -519,15 +514,10 @@ static void skl_detach_scaler(struct intel_crtc *crtc, int id)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
2022-02-24 16:51 ` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming Ville Syrjala
@ 2022-02-24 16:51 ` Ville Syrjala
2022-03-29 9:28 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair Ville Syrjala
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2022-02-24 16:51 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The ilk+ panel fitter register are sitting nicely on their own
cacheline, so no need for global serialization via uncore.lock.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7bf24df20b14..705f23be409c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1114,13 +1114,13 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
* e.g. x201.
*/
if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
- intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
- PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
+ intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
+ PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
else
- intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
- PF_FILTER_MED_3x3);
- intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
- intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
+ intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
+ PF_FILTER_MED_3x3);
+ intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
+ intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -2022,9 +2022,9 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->pch_pfit.enabled)
return;
- intel_de_write(dev_priv, PF_CTL(pipe), 0);
- intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
- intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
+ intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
+ intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
+ intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
}
static void ilk_crtc_disable(struct intel_atomic_state *state,
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
2022-02-24 16:51 ` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming Ville Syrjala
2022-02-24 16:51 ` [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked Ville Syrjala
@ 2022-02-24 16:51 ` Ville Syrjala
2022-03-29 9:29 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to " Ville Syrjala
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2022-02-24 16:51 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To reduce the amount of registers written during the vblank evade
critical section let's also split the .color_commit() hook to
noarm+arm pair. The noarm hook runs before the vblank evasion
with the arm hook staying inside the critical section.
Just the framework here, actually moving stuff out into the noarm
hook will follow.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 59 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_color.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++--
3 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e94ec57260f1..df775c6179b2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -31,12 +31,21 @@
struct intel_color_funcs {
int (*color_check)(struct intel_crtc_state *crtc_state);
/*
- * Program double buffered color management registers during
- * vblank evasion. The registers should then latch during the
- * next vblank start, alongside any other double buffered registers
- * involved with the same commit.
+ * Program non-arming double buffered color management registers
+ * before vblank evasion. The registers should then latch after
+ * the arming register is written (by color_commit_arm()) during
+ * the next vblank start, alongside any other double buffered
+ * registers involved with the same commit. This hook is optional.
*/
- void (*color_commit)(const struct intel_crtc_state *crtc_state);
+ void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state);
+ /*
+ * Program arming double buffered color management registers
+ * during vblank evasion. The registers (and whatever other registers
+ * they arm that were written by color_commit_noarm) should then latch
+ * during the next vblank start, alongside any other double buffered
+ * registers involved with the same commit.
+ */
+ void (*color_commit_arm)(const struct intel_crtc_state *crtc_state);
/*
* Load LUTs (and other single buffered color management
* registers). Will (hopefully) be called during the vblank
@@ -491,7 +500,7 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
}
-static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
+static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -504,7 +513,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, PIPECONF(pipe), val);
}
-static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
+static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -519,7 +528,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
ilk_load_csc_matrix(crtc_state);
}
-static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
+static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -530,7 +539,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
ilk_load_csc_matrix(crtc_state);
}
-static void skl_color_commit(const struct intel_crtc_state *crtc_state)
+static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1169,11 +1178,19 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
dev_priv->color_funcs->load_luts(crtc_state);
}
-void intel_color_commit(const struct intel_crtc_state *crtc_state)
+void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs->color_commit(crtc_state);
+ if (dev_priv->color_funcs->color_commit_noarm)
+ dev_priv->color_funcs->color_commit_noarm(crtc_state);
+}
+
+void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
+ dev_priv->color_funcs->color_commit_arm(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -2132,70 +2149,70 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
- .color_commit = i9xx_color_commit,
+ .color_commit_arm = i9xx_color_commit_arm,
.load_luts = chv_load_luts,
.read_luts = chv_read_luts,
};
static const struct intel_color_funcs i965_color_funcs = {
.color_check = i9xx_color_check,
- .color_commit = i9xx_color_commit,
+ .color_commit_arm = i9xx_color_commit_arm,
.load_luts = i965_load_luts,
.read_luts = i965_read_luts,
};
static const struct intel_color_funcs i9xx_color_funcs = {
.color_check = i9xx_color_check,
- .color_commit = i9xx_color_commit,
+ .color_commit_arm = i9xx_color_commit_arm,
.load_luts = i9xx_load_luts,
.read_luts = i9xx_read_luts,
};
static const struct intel_color_funcs icl_color_funcs = {
.color_check = icl_color_check,
- .color_commit = skl_color_commit,
+ .color_commit_arm = skl_color_commit_arm,
.load_luts = icl_load_luts,
.read_luts = icl_read_luts,
};
static const struct intel_color_funcs glk_color_funcs = {
.color_check = glk_color_check,
- .color_commit = skl_color_commit,
+ .color_commit_arm = skl_color_commit_arm,
.load_luts = glk_load_luts,
.read_luts = glk_read_luts,
};
static const struct intel_color_funcs skl_color_funcs = {
.color_check = ivb_color_check,
- .color_commit = skl_color_commit,
+ .color_commit_arm = skl_color_commit_arm,
.load_luts = bdw_load_luts,
.read_luts = NULL,
};
static const struct intel_color_funcs bdw_color_funcs = {
.color_check = ivb_color_check,
- .color_commit = hsw_color_commit,
+ .color_commit_arm = hsw_color_commit_arm,
.load_luts = bdw_load_luts,
.read_luts = NULL,
};
static const struct intel_color_funcs hsw_color_funcs = {
.color_check = ivb_color_check,
- .color_commit = hsw_color_commit,
+ .color_commit_arm = hsw_color_commit_arm,
.load_luts = ivb_load_luts,
.read_luts = NULL,
};
static const struct intel_color_funcs ivb_color_funcs = {
.color_check = ivb_color_check,
- .color_commit = ilk_color_commit,
+ .color_commit_arm = ilk_color_commit_arm,
.load_luts = ivb_load_luts,
.read_luts = NULL,
};
static const struct intel_color_funcs ilk_color_funcs = {
.color_check = ilk_color_check,
- .color_commit = ilk_color_commit,
+ .color_commit_arm = ilk_color_commit_arm,
.load_luts = ilk_load_luts,
.read_luts = ilk_read_luts,
};
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 173727aaa24d..fd873425e082 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -14,7 +14,8 @@ struct drm_property_blob;
void intel_color_init(struct intel_crtc *crtc);
int intel_color_check(struct intel_crtc_state *crtc_state);
-void intel_color_commit(const struct intel_crtc_state *crtc_state);
+void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
+void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
void intel_color_get_config(struct intel_crtc_state *crtc_state);
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 705f23be409c..741f5249db6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1778,7 +1778,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
* clocks enabled
*/
intel_color_load_luts(new_crtc_state);
- intel_color_commit(new_crtc_state);
+ intel_color_commit_noarm(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
@@ -1969,7 +1970,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
* clocks enabled
*/
intel_color_load_luts(new_crtc_state);
- intel_color_commit(new_crtc_state);
+ intel_color_commit_noarm(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
if (DISPLAY_VER(dev_priv) < 9)
intel_disable_primary_plane(new_crtc_state);
@@ -2389,7 +2391,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
i9xx_pfit_enable(new_crtc_state);
intel_color_load_luts(new_crtc_state);
- intel_color_commit(new_crtc_state);
+ intel_color_commit_noarm(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
@@ -2428,7 +2431,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
i9xx_pfit_enable(new_crtc_state);
intel_color_load_luts(new_crtc_state);
- intel_color_commit(new_crtc_state);
+ intel_color_commit_noarm(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
@@ -7897,7 +7901,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
if (!modeset) {
if (new_crtc_state->uapi.color_mgmt_changed ||
new_crtc_state->update_pipe)
- intel_color_commit(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
@@ -7977,6 +7981,11 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_fbc_update(state, crtc);
+ if (!modeset &&
+ (new_crtc_state->uapi.color_mgmt_changed ||
+ new_crtc_state->update_pipe))
+ intel_color_commit_noarm(new_crtc_state);
+
intel_crtc_planes_update_noarm(state, crtc);
/* Perform vblank evasion around commit operation */
@@ -9880,7 +9889,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
}
/* Disable any background color/etc. set by the BIOS */
- intel_color_commit(crtc_state);
+ intel_color_commit_noarm(crtc_state);
+ intel_color_commit_arm(crtc_state);
}
/* Adjust the state of the output pipe according to whether we
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to noarm+arm pair
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
` (2 preceding siblings ...)
2022-02-24 16:51 ` [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair Ville Syrjala
@ 2022-02-24 16:51 ` Ville Syrjala
2022-03-29 9:29 ` Lisovskiy, Stanislav
2022-02-25 3:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+ Patchwork
2022-02-25 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2022-02-24 16:51 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move most of the pipe+output CSC programming to the
.color_commit_noarm() hook which runs before vblank evasion.
Only PIPE_CSC_MODE (the arming register) needs to remain in
inside the critical section.
A test case that just updates the CTM in a loop produces
the following i915_update_info numbers on ilk (w/o lockdep):
old new
Updates: 10012 Updates: 10008
| |
1us |** 1us |**********
|************* |*************
4us |********* 4us |*
|* |**
16us | 16us |
| |
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 1345ns Min update: 1268ns
Max update: 16672ns Max update: 15656ns
Average update: 3914ns Average update: 2185ns
Overruns > 100us: 0 Overruns > 100us: 0
And here is tgl (forced to update both pipe CSC and
output CSC, and with lockdep enabled):
old new
Updates: 10012 Updates: 10012
| |
1us | 1us |
| |
4us |* 4us |**
|** |**********
16us |************* 16us |*************
|* |
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 5204ns Min update: 5176ns
Max update: 176038ns Max update: 186685ns
Average update: 23931ns Average update: 16654ns
Overruns > 250us: 0 Overruns > 250us: 0
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 36 ++++++++++++++--------
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index df775c6179b2..34128c9c635c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -346,15 +346,11 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
ilk_csc_coeff_identity,
ilk_csc_off_zero);
}
-
- intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
- crtc_state->csc_mode);
}
static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (crtc_state->hw.ctm) {
u16 coeff[9];
@@ -373,9 +369,6 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
ilk_csc_coeff_limited_range,
ilk_csc_postoff_limited_range);
}
-
- intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
- crtc_state->csc_mode);
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
@@ -500,6 +493,16 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
}
+static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
+{
+ icl_load_csc_matrix(crtc_state);
+}
+
+static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
+{
+ ilk_load_csc_matrix(crtc_state);
+}
+
static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -525,7 +528,8 @@ static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
intel_de_write(dev_priv, PIPECONF(pipe), val);
- ilk_load_csc_matrix(crtc_state);
+ intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe),
+ crtc_state->csc_mode);
}
static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
@@ -536,7 +540,8 @@ static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
crtc_state->gamma_mode);
- ilk_load_csc_matrix(crtc_state);
+ intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
+ crtc_state->csc_mode);
}
static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
@@ -560,10 +565,8 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
crtc_state->gamma_mode);
- if (DISPLAY_VER(dev_priv) >= 11)
- icl_load_csc_matrix(crtc_state);
- else
- ilk_load_csc_matrix(crtc_state);
+ intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
+ crtc_state->csc_mode);
}
static void i9xx_load_lut_8(struct intel_crtc *crtc,
@@ -2170,6 +2173,7 @@ static const struct intel_color_funcs i9xx_color_funcs = {
static const struct intel_color_funcs icl_color_funcs = {
.color_check = icl_color_check,
+ .color_commit_noarm = icl_color_commit_noarm,
.color_commit_arm = skl_color_commit_arm,
.load_luts = icl_load_luts,
.read_luts = icl_read_luts,
@@ -2177,6 +2181,7 @@ static const struct intel_color_funcs icl_color_funcs = {
static const struct intel_color_funcs glk_color_funcs = {
.color_check = glk_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = skl_color_commit_arm,
.load_luts = glk_load_luts,
.read_luts = glk_read_luts,
@@ -2184,6 +2189,7 @@ static const struct intel_color_funcs glk_color_funcs = {
static const struct intel_color_funcs skl_color_funcs = {
.color_check = ivb_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = skl_color_commit_arm,
.load_luts = bdw_load_luts,
.read_luts = NULL,
@@ -2191,6 +2197,7 @@ static const struct intel_color_funcs skl_color_funcs = {
static const struct intel_color_funcs bdw_color_funcs = {
.color_check = ivb_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = hsw_color_commit_arm,
.load_luts = bdw_load_luts,
.read_luts = NULL,
@@ -2198,6 +2205,7 @@ static const struct intel_color_funcs bdw_color_funcs = {
static const struct intel_color_funcs hsw_color_funcs = {
.color_check = ivb_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = hsw_color_commit_arm,
.load_luts = ivb_load_luts,
.read_luts = NULL,
@@ -2205,6 +2213,7 @@ static const struct intel_color_funcs hsw_color_funcs = {
static const struct intel_color_funcs ivb_color_funcs = {
.color_check = ivb_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = ilk_color_commit_arm,
.load_luts = ivb_load_luts,
.read_luts = NULL,
@@ -2212,6 +2221,7 @@ static const struct intel_color_funcs ivb_color_funcs = {
static const struct intel_color_funcs ilk_color_funcs = {
.color_check = ilk_color_check,
+ .color_commit_noarm = ilk_color_commit_noarm,
.color_commit_arm = ilk_color_commit_arm,
.load_luts = ilk_load_luts,
.read_luts = ilk_read_luts,
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
` (3 preceding siblings ...)
2022-02-24 16:51 ` [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to " Ville Syrjala
@ 2022-02-25 3:34 ` Patchwork
2022-02-25 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-02-25 3:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9405 bytes --]
== Series Details ==
Series: drm/i915: Optimize CSC updates for ilk+
URL : https://patchwork.freedesktop.org/series/100693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22402
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (2): fi-kbl-soraka fi-pnv-d510
Missing (3): fi-bdw-samus fi-kbl-x1275 fi-kbl-guc
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22402:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_auth@basic-auth:
- {bat-jsl-2}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-jsl-2/igt@core_auth@basic-auth.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/bat-jsl-2/igt@core_auth@basic-auth.html
* igt@i915_selftest@live@hangcheck:
- {bat-jsl-2}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-jsl-2/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/bat-jsl-2/igt@i915_selftest@live@hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_22402 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-bxt-dsi: [PASS][5] -> [FAIL][6] ([i915#4912])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-bxt-dsi/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-bxt-dsi/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [PASS][12] -> [DMESG-FAIL][13] ([i915#5026])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-blb-e6850/igt@i915_selftest@live@gem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-blb-e6850/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][14] ([i915#1886] / [i915#2291])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][15] -> [INCOMPLETE][16] ([i915#3921])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][19] ([fdo#109271]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u: [PASS][20] -> [DMESG-WARN][21] ([i915#165]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][22] -> [DMESG-WARN][23] ([i915#165] / [i915#295]) +13 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#533])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: NOTRUN -> [FAIL][26] ([i915#4547])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][27] ([fdo#109271]) +57 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][28] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/fi-blb-e6850/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][29] ([i915#3576]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4912]: https://gitlab.freedesktop.org/drm/intel/issues/4912
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11285 -> Patchwork_22402
CI-20190529: 20190529
CI_DRM_11285: 937927c7022766ecf991e0071ae055412fb3805f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6357: 6546304ecf053b9c5ec278ee3c210d2c6d50a3a6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22402: 743afae0f8940330df5f0ad2c2cc572d297f50e2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
743afae0f894 drm/i915: Split pipe+output CSC programming to noarm+arm pair
92d184c4e369 drm/i915: Split color_commit() into noarm+arm pair
3440a114eac7 drm/i915: Make ilk+ pfit regiser unlocked
028903b226df drm/i915: Remove locks around skl+ scaler programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/index.html
[-- Attachment #2: Type: text/html, Size: 11490 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Optimize CSC updates for ilk+
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
` (4 preceding siblings ...)
2022-02-25 3:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+ Patchwork
@ 2022-02-25 19:27 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-02-25 19:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30263 bytes --]
== Series Details ==
Series: drm/i915: Optimize CSC updates for ilk+
URL : https://patchwork.freedesktop.org/series/100693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11285_full -> Patchwork_22402_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_22402_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-4x:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@feature_discovery@display-4x.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-snb7/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_exec_capture@pi@vcs0:
- shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([i915#3371])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-tglb7/igt@gem_exec_capture@pi@vcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-tglb1/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +107 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_schedule@smoketest@rcs0:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk5/igt@gem_exec_schedule@smoketest@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-glk8/igt@gem_exec_schedule@smoketest@rcs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#4270])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#768]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#3323])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#3297])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen7_exec_parse@basic-offset:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109289])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#2856])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109293] / [fdo#109506])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_sseu@full-enable:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#3048])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl10/igt@i915_pm_sseu@full-enable.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl9/igt@i915_pm_sseu@full-enable.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: NOTRUN -> [DMESG-WARN][27] ([i915#180])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl4/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][32] ([i915#3763])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +6 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271]) +51 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278] / [i915#3886]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#3742])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl6/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +5 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-a-ctm-negative:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +7 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-negative.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3359])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-512x170-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278] / [fdo#109279]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271]) +77 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl6/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278]) +13 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274] / [fdo#109278]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2346])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][52] -> [DMESG-WARN][53] ([i915#180]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][54] -> [SKIP][55] ([i915#3701])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109280]) +7 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_hdr@static-toggle:
- shard-iclb: NOTRUN -> [SKIP][57] ([i915#1187])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_hdr@static-toggle.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109642] / [fdo#111068] / [i915#658])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][66] -> [SKIP][67] ([fdo#109441]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109441])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@kms_psr@psr2_dpms.html
* igt@kms_psr@sprite_blt:
- shard-snb: NOTRUN -> [SKIP][69] ([fdo#109271]) +36 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-snb7/igt@kms_psr@sprite_blt.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2437])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#2530])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling:
- shard-skl: [PASS][72] -> [FAIL][73] ([i915#1542])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl7/igt@perf@polling.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl7/igt@perf@polling.html
* igt@perf@polling-parameterized:
- shard-skl: NOTRUN -> [FAIL][74] ([i915#1542])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl1/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_self_import:
- shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109291])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@prime_nv_api@i915_self_import.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109295])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-10:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@sysfs_clients@split-10.html
* igt@sysfs_clients@split-50:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2994])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][80] ([i915#2842]) -> [PASS][81] +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [FAIL][82] ([i915#2842]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-snb: [SKIP][84] ([fdo#109271]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-snb6/igt@gem_exec_suspend@basic-s3@smem.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-snb7/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][86] ([i915#454]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][88] ([i915#3921]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-snb6/igt@i915_selftest@live@hangcheck.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][90] ([i915#180] / [i915#636]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][92] ([i915#180]) -> [PASS][93] +6 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][96] ([i915#2122]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][98] ([i915#4911]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][100] ([i915#1188]) -> [PASS][101] +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* {igt@kms_plane_scaling@upscale-with-rotation-factor-4@pipe-a-upscale-with-rotation}:
- shard-skl: [DMESG-WARN][102] ([i915#1982]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl6/igt@kms_plane_scaling@upscale-with-rotation-factor-4@pipe-a-upscale-with-rotation.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-skl6/igt@kms_plane_scaling@upscale-with-rotation-factor-4@pipe-a-upscale-with-rotation.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][104] ([fdo#109441]) -> [PASS][105] +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][106] ([i915#31]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk2/igt@kms_setmode@basic.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-glk6/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [DMESG-WARN][108] ([i915#5076]) -> [SKIP][109] ([i915#4525]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb5/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][110] ([i915#4525]) -> [DMESG-FAIL][111] ([i915#5076])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][112] ([i915#4525]) -> [DMESG-WARN][113] ([i915#5076]) +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][114] ([i915#2684]) -> [WARN][115] ([i915#1804] / [i915#2684])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][116] ([fdo#111068] / [i915#658]) -> [SKIP][117] ([i915#2920])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#4312] / [i915#92]) -> ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150]) ([i915#1436] / [i915#180] / [i915#2426] / [i915#3002] / [i915#4312])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl6/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl4/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl6/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl4/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl6/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl4/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl3/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl3/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl4/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl3/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl4/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl4/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl1/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl6/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl6/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/shard-kbl7/igt@runner@aborted.html
- shard-skl: ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155]) ([i915#1436] / [i915#2029] / [i915#2426] / [i915#3002] / [i915#4312]) -> ([FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159]) ([i915#1436] / [i915#2426] / [i915#3002] / [i915#4312])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl4/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-skl3/igt@runner@aborted.html
[153]: https:/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22402/index.html
[-- Attachment #2: Type: text/html, Size: 33764 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming
2022-02-24 16:51 ` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming Ville Syrjala
@ 2022-03-29 9:28 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 11+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-29 9:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Feb 24, 2022 at 06:51:00PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the skl+ scaler registers are suitably confined to their own
> cachelines so we don't need the uncore.lock to globally serialize
> access to these registers. We actually already dropped some of this
> in commit 14ad15296d1f ("drm/i915: Make skl+ universal plane
> registers unlocked") as the plane scaler enabling/reconfiguration
> became lockless. So let's complete that and remove the rest of
> the locks from the scaler programming as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index c2e94118566b..ac67e9fbb713 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -412,7 +412,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> int x = dst->x1;
> int y = dst->y1;
> int hscale, vscale;
> - unsigned long irqflags;
> int id;
> u32 ps_ctrl;
>
> @@ -434,8 +433,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
> ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
>
> - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> -
> skl_scaler_setup_filter(dev_priv, pipe, id, 0,
> crtc_state->hw.scaling_filter);
>
> @@ -449,8 +446,6 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> x << 16 | y);
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> width << 16 | height);
> -
> - spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> void
> @@ -519,15 +514,10 @@ static void skl_detach_scaler(struct intel_crtc *crtc, int id)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - unsigned long irqflags;
> -
> - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
> intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
> -
> - spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> /*
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked
2022-02-24 16:51 ` [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked Ville Syrjala
@ 2022-03-29 9:28 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 11+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-29 9:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Feb 24, 2022 at 06:51:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The ilk+ panel fitter register are sitting nicely on their own
> cacheline, so no need for global serialization via uncore.lock.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7bf24df20b14..705f23be409c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1114,13 +1114,13 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> * e.g. x201.
> */
> if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> - intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
> - PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
> + intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> + PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
> else
> - intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
> - PF_FILTER_MED_3x3);
> - intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> - intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> + intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> + PF_FILTER_MED_3x3);
> + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> }
>
> static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -2022,9 +2022,9 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> if (!old_crtc_state->pch_pfit.enabled)
> return;
>
> - intel_de_write(dev_priv, PF_CTL(pipe), 0);
> - intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
> - intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
> + intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
> + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
> + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
> }
>
> static void ilk_crtc_disable(struct intel_atomic_state *state,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to noarm+arm pair
2022-02-24 16:51 ` [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to " Ville Syrjala
@ 2022-03-29 9:29 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 11+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-29 9:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Feb 24, 2022 at 06:51:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move most of the pipe+output CSC programming to the
> .color_commit_noarm() hook which runs before vblank evasion.
> Only PIPE_CSC_MODE (the arming register) needs to remain in
> inside the critical section.
>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> A test case that just updates the CTM in a loop produces
> the following i915_update_info numbers on ilk (w/o lockdep):
> old new
> Updates: 10012 Updates: 10008
> | |
> 1us |** 1us |**********
> |************* |*************
> 4us |********* 4us |*
> |* |**
> 16us | 16us |
> | |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 1345ns Min update: 1268ns
> Max update: 16672ns Max update: 15656ns
> Average update: 3914ns Average update: 2185ns
> Overruns > 100us: 0 Overruns > 100us: 0
>
> And here is tgl (forced to update both pipe CSC and
> output CSC, and with lockdep enabled):
> old new
> Updates: 10012 Updates: 10012
> | |
> 1us | 1us |
> | |
> 4us |* 4us |**
> |** |**********
> 16us |************* 16us |*************
> |* |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 5204ns Min update: 5176ns
> Max update: 176038ns Max update: 186685ns
> Average update: 23931ns Average update: 16654ns
> Overruns > 250us: 0 Overruns > 250us: 0
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 36 ++++++++++++++--------
> 1 file changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index df775c6179b2..34128c9c635c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -346,15 +346,11 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> ilk_csc_coeff_identity,
> ilk_csc_off_zero);
> }
> -
> - intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> - crtc_state->csc_mode);
> }
>
> static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (crtc_state->hw.ctm) {
> u16 coeff[9];
> @@ -373,9 +369,6 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> ilk_csc_coeff_limited_range,
> ilk_csc_postoff_limited_range);
> }
> -
> - intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> - crtc_state->csc_mode);
> }
>
> static void chv_load_cgm_csc(struct intel_crtc *crtc,
> @@ -500,6 +493,16 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
> }
>
> +static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> +{
> + icl_load_csc_matrix(crtc_state);
> +}
> +
> +static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> +{
> + ilk_load_csc_matrix(crtc_state);
> +}
> +
> static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -525,7 +528,8 @@ static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
> val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> intel_de_write(dev_priv, PIPECONF(pipe), val);
>
> - ilk_load_csc_matrix(crtc_state);
> + intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe),
> + crtc_state->csc_mode);
> }
>
> static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
> @@ -536,7 +540,8 @@ static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
> crtc_state->gamma_mode);
>
> - ilk_load_csc_matrix(crtc_state);
> + intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> + crtc_state->csc_mode);
> }
>
> static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
> @@ -560,10 +565,8 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
> crtc_state->gamma_mode);
>
> - if (DISPLAY_VER(dev_priv) >= 11)
> - icl_load_csc_matrix(crtc_state);
> - else
> - ilk_load_csc_matrix(crtc_state);
> + intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
> + crtc_state->csc_mode);
> }
>
> static void i9xx_load_lut_8(struct intel_crtc *crtc,
> @@ -2170,6 +2173,7 @@ static const struct intel_color_funcs i9xx_color_funcs = {
>
> static const struct intel_color_funcs icl_color_funcs = {
> .color_check = icl_color_check,
> + .color_commit_noarm = icl_color_commit_noarm,
> .color_commit_arm = skl_color_commit_arm,
> .load_luts = icl_load_luts,
> .read_luts = icl_read_luts,
> @@ -2177,6 +2181,7 @@ static const struct intel_color_funcs icl_color_funcs = {
>
> static const struct intel_color_funcs glk_color_funcs = {
> .color_check = glk_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = skl_color_commit_arm,
> .load_luts = glk_load_luts,
> .read_luts = glk_read_luts,
> @@ -2184,6 +2189,7 @@ static const struct intel_color_funcs glk_color_funcs = {
>
> static const struct intel_color_funcs skl_color_funcs = {
> .color_check = ivb_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = skl_color_commit_arm,
> .load_luts = bdw_load_luts,
> .read_luts = NULL,
> @@ -2191,6 +2197,7 @@ static const struct intel_color_funcs skl_color_funcs = {
>
> static const struct intel_color_funcs bdw_color_funcs = {
> .color_check = ivb_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = hsw_color_commit_arm,
> .load_luts = bdw_load_luts,
> .read_luts = NULL,
> @@ -2198,6 +2205,7 @@ static const struct intel_color_funcs bdw_color_funcs = {
>
> static const struct intel_color_funcs hsw_color_funcs = {
> .color_check = ivb_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = hsw_color_commit_arm,
> .load_luts = ivb_load_luts,
> .read_luts = NULL,
> @@ -2205,6 +2213,7 @@ static const struct intel_color_funcs hsw_color_funcs = {
>
> static const struct intel_color_funcs ivb_color_funcs = {
> .color_check = ivb_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = ilk_color_commit_arm,
> .load_luts = ivb_load_luts,
> .read_luts = NULL,
> @@ -2212,6 +2221,7 @@ static const struct intel_color_funcs ivb_color_funcs = {
>
> static const struct intel_color_funcs ilk_color_funcs = {
> .color_check = ilk_color_check,
> + .color_commit_noarm = ilk_color_commit_noarm,
> .color_commit_arm = ilk_color_commit_arm,
> .load_luts = ilk_load_luts,
> .read_luts = ilk_read_luts,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair
2022-02-24 16:51 ` [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair Ville Syrjala
@ 2022-03-29 9:29 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 11+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-29 9:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Feb 24, 2022 at 06:51:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To reduce the amount of registers written during the vblank evade
> critical section let's also split the .color_commit() hook to
> noarm+arm pair. The noarm hook runs before the vblank evasion
> with the arm hook staying inside the critical section.
>
> Just the framework here, actually moving stuff out into the noarm
> hook will follow.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 59 +++++++++++++-------
> drivers/gpu/drm/i915/display/intel_color.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++--
> 3 files changed, 56 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index e94ec57260f1..df775c6179b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -31,12 +31,21 @@
> struct intel_color_funcs {
> int (*color_check)(struct intel_crtc_state *crtc_state);
> /*
> - * Program double buffered color management registers during
> - * vblank evasion. The registers should then latch during the
> - * next vblank start, alongside any other double buffered registers
> - * involved with the same commit.
> + * Program non-arming double buffered color management registers
> + * before vblank evasion. The registers should then latch after
> + * the arming register is written (by color_commit_arm()) during
> + * the next vblank start, alongside any other double buffered
> + * registers involved with the same commit. This hook is optional.
> */
> - void (*color_commit)(const struct intel_crtc_state *crtc_state);
> + void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state);
> + /*
> + * Program arming double buffered color management registers
> + * during vblank evasion. The registers (and whatever other registers
> + * they arm that were written by color_commit_noarm) should then latch
> + * during the next vblank start, alongside any other double buffered
> + * registers involved with the same commit.
> + */
> + void (*color_commit_arm)(const struct intel_crtc_state *crtc_state);
> /*
> * Load LUTs (and other single buffered color management
> * registers). Will (hopefully) be called during the vblank
> @@ -491,7 +500,7 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
> }
>
> -static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> +static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -504,7 +513,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, PIPECONF(pipe), val);
> }
>
> -static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> +static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -519,7 +528,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> -static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> +static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -530,7 +539,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> -static void skl_color_commit(const struct intel_crtc_state *crtc_state)
> +static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1169,11 +1178,19 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> dev_priv->color_funcs->load_luts(crtc_state);
> }
>
> -void intel_color_commit(const struct intel_crtc_state *crtc_state)
> +void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - dev_priv->color_funcs->color_commit(crtc_state);
> + if (dev_priv->color_funcs->color_commit_noarm)
> + dev_priv->color_funcs->color_commit_noarm(crtc_state);
> +}
> +
> +void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +
> + dev_priv->color_funcs->color_commit_arm(crtc_state);
> }
>
> static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
> @@ -2132,70 +2149,70 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
>
> static const struct intel_color_funcs chv_color_funcs = {
> .color_check = chv_color_check,
> - .color_commit = i9xx_color_commit,
> + .color_commit_arm = i9xx_color_commit_arm,
> .load_luts = chv_load_luts,
> .read_luts = chv_read_luts,
> };
>
> static const struct intel_color_funcs i965_color_funcs = {
> .color_check = i9xx_color_check,
> - .color_commit = i9xx_color_commit,
> + .color_commit_arm = i9xx_color_commit_arm,
> .load_luts = i965_load_luts,
> .read_luts = i965_read_luts,
> };
>
> static const struct intel_color_funcs i9xx_color_funcs = {
> .color_check = i9xx_color_check,
> - .color_commit = i9xx_color_commit,
> + .color_commit_arm = i9xx_color_commit_arm,
> .load_luts = i9xx_load_luts,
> .read_luts = i9xx_read_luts,
> };
>
> static const struct intel_color_funcs icl_color_funcs = {
> .color_check = icl_color_check,
> - .color_commit = skl_color_commit,
> + .color_commit_arm = skl_color_commit_arm,
> .load_luts = icl_load_luts,
> .read_luts = icl_read_luts,
> };
>
> static const struct intel_color_funcs glk_color_funcs = {
> .color_check = glk_color_check,
> - .color_commit = skl_color_commit,
> + .color_commit_arm = skl_color_commit_arm,
> .load_luts = glk_load_luts,
> .read_luts = glk_read_luts,
> };
>
> static const struct intel_color_funcs skl_color_funcs = {
> .color_check = ivb_color_check,
> - .color_commit = skl_color_commit,
> + .color_commit_arm = skl_color_commit_arm,
> .load_luts = bdw_load_luts,
> .read_luts = NULL,
> };
>
> static const struct intel_color_funcs bdw_color_funcs = {
> .color_check = ivb_color_check,
> - .color_commit = hsw_color_commit,
> + .color_commit_arm = hsw_color_commit_arm,
> .load_luts = bdw_load_luts,
> .read_luts = NULL,
> };
>
> static const struct intel_color_funcs hsw_color_funcs = {
> .color_check = ivb_color_check,
> - .color_commit = hsw_color_commit,
> + .color_commit_arm = hsw_color_commit_arm,
> .load_luts = ivb_load_luts,
> .read_luts = NULL,
> };
>
> static const struct intel_color_funcs ivb_color_funcs = {
> .color_check = ivb_color_check,
> - .color_commit = ilk_color_commit,
> + .color_commit_arm = ilk_color_commit_arm,
> .load_luts = ivb_load_luts,
> .read_luts = NULL,
> };
>
> static const struct intel_color_funcs ilk_color_funcs = {
> .color_check = ilk_color_check,
> - .color_commit = ilk_color_commit,
> + .color_commit_arm = ilk_color_commit_arm,
> .load_luts = ilk_load_luts,
> .read_luts = ilk_read_luts,
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
> index 173727aaa24d..fd873425e082 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.h
> +++ b/drivers/gpu/drm/i915/display/intel_color.h
> @@ -14,7 +14,8 @@ struct drm_property_blob;
>
> void intel_color_init(struct intel_crtc *crtc);
> int intel_color_check(struct intel_crtc_state *crtc_state);
> -void intel_color_commit(const struct intel_crtc_state *crtc_state);
> +void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
> +void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
> void intel_color_get_config(struct intel_crtc_state *crtc_state);
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 705f23be409c..741f5249db6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1778,7 +1778,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
> * clocks enabled
> */
> intel_color_load_luts(new_crtc_state);
> - intel_color_commit(new_crtc_state);
> + intel_color_commit_noarm(new_crtc_state);
> + intel_color_commit_arm(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> @@ -1969,7 +1970,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> * clocks enabled
> */
> intel_color_load_luts(new_crtc_state);
> - intel_color_commit(new_crtc_state);
> + intel_color_commit_noarm(new_crtc_state);
> + intel_color_commit_arm(new_crtc_state);
> /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> if (DISPLAY_VER(dev_priv) < 9)
> intel_disable_primary_plane(new_crtc_state);
> @@ -2389,7 +2391,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
> i9xx_pfit_enable(new_crtc_state);
>
> intel_color_load_luts(new_crtc_state);
> - intel_color_commit(new_crtc_state);
> + intel_color_commit_noarm(new_crtc_state);
> + intel_color_commit_arm(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> @@ -2428,7 +2431,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
> i9xx_pfit_enable(new_crtc_state);
>
> intel_color_load_luts(new_crtc_state);
> - intel_color_commit(new_crtc_state);
> + intel_color_commit_noarm(new_crtc_state);
> + intel_color_commit_arm(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> @@ -7897,7 +7901,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> if (!modeset) {
> if (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe)
> - intel_color_commit(new_crtc_state);
> + intel_color_commit_arm(new_crtc_state);
>
> if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(new_crtc_state);
> @@ -7977,6 +7981,11 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> intel_fbc_update(state, crtc);
>
> + if (!modeset &&
> + (new_crtc_state->uapi.color_mgmt_changed ||
> + new_crtc_state->update_pipe))
> + intel_color_commit_noarm(new_crtc_state);
> +
> intel_crtc_planes_update_noarm(state, crtc);
>
> /* Perform vblank evasion around commit operation */
> @@ -9880,7 +9889,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
> }
>
> /* Disable any background color/etc. set by the BIOS */
> - intel_color_commit(crtc_state);
> + intel_color_commit_noarm(crtc_state);
> + intel_color_commit_arm(crtc_state);
> }
>
> /* Adjust the state of the output pipe according to whether we
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-03-29 9:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-24 16:50 [Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+ Ville Syrjala
2022-02-24 16:51 ` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming Ville Syrjala
2022-03-29 9:28 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked Ville Syrjala
2022-03-29 9:28 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair Ville Syrjala
2022-03-29 9:29 ` Lisovskiy, Stanislav
2022-02-24 16:51 ` [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to " Ville Syrjala
2022-03-29 9:29 ` Lisovskiy, Stanislav
2022-02-25 3:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+ Patchwork
2022-02-25 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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