[PATCH 5/5] mmc: sdhci-brcmstb: Add ability to increase max clock rate for 72116b0

[Kamal Dasu <kdasu.kdev@gmail.com>]

From: Al Cooper <alcooperx@gmail.com>

The 72116B0 has improved SDIO controllers that allow the max clock
rate to be increased from a max of 100MHz to a max of 150MHz. The
driver will need to get the clock and increase it's default rate
and override the caps register, that still indicates a max of 100MHz.
The new clock will be named "sdio_freq" in the DT node's "clock-names"
list. The driver will use a DT property, "clock-frequency", to
enable this functionality and will get the actual rate in MHz
from the property to allow various speeds to be requested.

Signed-off-by: Al Cooper <alcooperx@gmail.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index d5cb3e8978b2..4f3629a8e70a 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -250,6 +250,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 	struct sdhci_pltfm_host *pltfm_host;
 	const struct of_device_id *match;
 	struct sdhci_brcmstb_priv *priv;
+	uint32_t base_clock_hz = 0;
 	struct sdhci_host *host;
 	struct resource *iomem;
 	struct clk *clk;
@@ -330,6 +331,30 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 	if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)
 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
+	/* Change the base clock frequency if the DT property exists */
+	if (device_property_read_u32(&pdev->dev, "clock-frequency",
+				     &base_clock_hz) == 0) {
+		struct clk *master_clk;
+		u32 actual_clock_mhz;
+
+		master_clk = devm_clk_get(&pdev->dev, "sdio_freq");
+		if (IS_ERR(master_clk)) {
+			dev_warn(&pdev->dev,
+				 "Clock for \"sdio_freq\" was not found\n");
+		} else {
+			clk_set_rate(master_clk, base_clock_hz);
+			actual_clock_mhz = clk_get_rate(master_clk) / 1000000;
+
+			host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
+			host->caps |=
+				(actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);
+			/* Disable presets because they are now incorrect */
+			host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+			dev_dbg(&pdev->dev,
+				"Base Clock Frequency changed to %dMHz\n",
+				actual_clock_mhz);
+		}
+	}
 	res = sdhci_brcmstb_add_host(host, priv);
 	if (res)
 		goto err;
-- 
2.17.1