From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 2/7] target/xtensa: use tcg_contatnt_* for numeric literals
Date: Fri, 22 Apr 2022 04:43:27 -0700 [thread overview]
Message-ID: <20220422114332.374472-3-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20220422114332.374472-1-jcmvbkbc@gmail.com>
Replace tcg_const_* for numeric literals with tcg_constant_*.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/translate.c | 28 +++++++++-------------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 9ecbbf172114..53f75f7586b2 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -306,16 +306,14 @@ static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
- TCGv_i32 tmp = tcg_const_i32(32);
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
- tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
+ tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
- tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
@@ -1956,11 +1954,10 @@ static void translate_mov(DisasContext *dc, const OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
- tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
@@ -1972,7 +1969,7 @@ static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@@ -1980,7 +1977,6 @@ static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
- tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
@@ -6443,7 +6439,7 @@ static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6455,7 +6451,6 @@ static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
- tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6475,7 +6470,7 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6489,7 +6484,6 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
- tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6665,14 +6659,13 @@ static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
- tcg_temp_free_i64(zero);
tcg_temp_free_i64(arg2);
}
@@ -6680,12 +6673,11 @@ static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
- tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
@@ -6694,7 +6686,7 @@ static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i32 tmp1 = tcg_temp_new_i32();
TCGv_i64 tmp2 = tcg_temp_new_i64();
@@ -6703,7 +6695,6 @@ static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movcond_i64(par[0],
arg[0].out, tmp2, zero,
arg[1].in, arg[0].in);
- tcg_temp_free_i64(zero);
tcg_temp_free_i32(tmp1);
tcg_temp_free_i64(tmp2);
}
@@ -6712,7 +6703,7 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@@ -6720,7 +6711,6 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
- tcg_temp_free(zero);
} else {
translate_movp_d(dc, arg, par);
}
--
2.30.2
next prev parent reply other threads:[~2022-04-22 12:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 11:43 [PATCH v2 0/7] target/xtensa: use tcg_constant_* where possible Max Filippov
2022-04-22 11:43 ` [PATCH v2 1/7] target/xtensa: fix missing tcg_temp_free in gen_window_check Max Filippov
2022-04-22 15:25 ` Richard Henderson
2022-04-22 11:43 ` Max Filippov [this message]
2022-04-22 11:43 ` [PATCH v2 3/7] target/xtensa: use tcg_constant_* for exceptions Max Filippov
2022-04-22 15:25 ` Richard Henderson
2022-04-22 11:43 ` [PATCH v2 4/7] target/xtensa: use tcg_constant_* for TLB opcodes Max Filippov
2022-04-22 11:43 ` [PATCH v2 5/7] target/xtensa: use tcg_constant_* for numbered special registers Max Filippov
2022-04-22 11:43 ` [PATCH v2 6/7] target/xtensa: use tcg_constant_* for FPU conversion opcodes Max Filippov
2022-04-22 11:43 ` [PATCH v2 7/7] target/xtensa: use tcg_constant_* for remaining opcodes Max Filippov
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