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From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 5/7] target/xtensa: use tcg_constant_* for numbered special registers
Date: Fri, 22 Apr 2022 04:43:30 -0700	[thread overview]
Message-ID: <20220422114332.374472-6-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20220422114332.374472-1-jcmvbkbc@gmail.com>

Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/translate.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 245c5968bd5d..c51aea460160 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2612,15 +2612,13 @@ static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     uint32_t id = par[0] - CCOMPARE;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->nccompare);
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_start();
     }
     tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
-    gen_helper_update_ccompare(cpu_env, tmp);
-    tcg_temp_free(tmp);
+    gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
 #endif
 }
 
@@ -2640,11 +2638,9 @@ static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - DBREAKA;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->ndbreak);
-    gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
@@ -2653,11 +2649,9 @@ static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - DBREAKC;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->ndbreak);
-    gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
@@ -2666,11 +2660,9 @@ static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - IBREAKA;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->nibreak);
-    gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
-- 
2.30.2



  parent reply	other threads:[~2022-04-22 12:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 11:43 [PATCH v2 0/7] target/xtensa: use tcg_constant_* where possible Max Filippov
2022-04-22 11:43 ` [PATCH v2 1/7] target/xtensa: fix missing tcg_temp_free in gen_window_check Max Filippov
2022-04-22 15:25   ` Richard Henderson
2022-04-22 11:43 ` [PATCH v2 2/7] target/xtensa: use tcg_contatnt_* for numeric literals Max Filippov
2022-04-22 11:43 ` [PATCH v2 3/7] target/xtensa: use tcg_constant_* for exceptions Max Filippov
2022-04-22 15:25   ` Richard Henderson
2022-04-22 11:43 ` [PATCH v2 4/7] target/xtensa: use tcg_constant_* for TLB opcodes Max Filippov
2022-04-22 11:43 ` Max Filippov [this message]
2022-04-22 11:43 ` [PATCH v2 6/7] target/xtensa: use tcg_constant_* for FPU conversion opcodes Max Filippov
2022-04-22 11:43 ` [PATCH v2 7/7] target/xtensa: use tcg_constant_* for remaining opcodes Max Filippov

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