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From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
Date: Fri, 29 Apr 2022 09:04:07 +0530	[thread overview]
Message-ID: <20220429033409.258707-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220429033409.258707-1-apatel@ventanamicro.com>

Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 target/riscv/cpu_helper.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1aa4f2097..d83579accf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 /* Trap into HS mode */
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
-                write_gva = false;
             }
             env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
         }
-- 
2.34.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Anup Patel <apatel@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Atish Patra <atishp@atishpatra.org>
Subject: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
Date: Fri, 29 Apr 2022 09:04:07 +0530	[thread overview]
Message-ID: <20220429033409.258707-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220429033409.258707-1-apatel@ventanamicro.com>

Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 target/riscv/cpu_helper.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1aa4f2097..d83579accf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 /* Trap into HS mode */
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
-                write_gva = false;
             }
             env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
         }
-- 
2.34.1



  parent reply	other threads:[~2022-04-29  3:34 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-29  3:34 [PATCH 0/4] QEMU RISC-V nested virtualization fixes Anup Patel
2022-04-29  3:34 ` Anup Patel
2022-04-29  3:34 ` [PATCH 1/4] target/riscv: Fix csr number based privilege checking Anup Patel
2022-04-29  3:34   ` Anup Patel
2022-04-29 10:54   ` Alistair Francis
2022-04-29 10:54     ` Alistair Francis
2022-04-30  3:19   ` Frank Chang
2022-04-30  3:19     ` Frank Chang
2022-05-09 19:13     ` Atish Patra
2022-04-29  3:34 ` Anup Patel [this message]
2022-04-29  3:34   ` [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Anup Patel
2022-05-05  9:51   ` Alistair Francis
2022-05-05 10:36     ` Anup Patel
2022-05-09  9:23       ` Alistair Francis
2022-05-09 12:00         ` Anup Patel
2022-04-29  3:34 ` [PATCH 3/4] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Anup Patel
2022-04-29  3:34   ` Anup Patel
2022-04-30  3:16   ` Frank Chang
2022-04-30  3:16     ` Frank Chang
2022-05-09  9:36   ` Alistair Francis
2022-04-29  3:34 ` [PATCH 4/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Anup Patel
2022-04-29  3:34   ` Anup Patel

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