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From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, Jason Gunthorpe <jgg@nvidia.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Kevin Tian <kevin.tian@intel.com>
Cc: iommu@lists.linux-foundation.org,
	Jacob jun Pan <jacob.jun.pan@intel.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH 5/5] iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
Date: Sun,  1 May 2022 19:24:34 +0800	[thread overview]
Message-ID: <20220501112434.874236-6-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20220501112434.874236-1-baolu.lu@linux.intel.com>

As enforce_cache_coherency has been introduced into the iommu_domain_ops,
the kernel component which owns the iommu domain is able to opt-in its
requirement for force snooping support. The iommu driver has no need to
hard code the page snoop control bit in the PASID table entries anymore.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/pasid.h | 1 -
 drivers/iommu/intel/iommu.c | 3 ---
 drivers/iommu/intel/pasid.c | 6 ------
 3 files changed, 10 deletions(-)

diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 583ea67fc783..394e6284ce1f 100644
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -48,7 +48,6 @@
  */
 #define PASID_FLAG_SUPERVISOR_MODE	BIT(0)
 #define PASID_FLAG_NESTED		BIT(1)
-#define PASID_FLAG_PAGE_SNOOP		BIT(2)
 
 /*
  * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index d5808495eb64..edd3d940eb25 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2432,9 +2432,6 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
 	if (level == 5)
 		flags |= PASID_FLAG_FL5LP;
 
-	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
-		flags |= PASID_FLAG_PAGE_SNOOP;
-
 	return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
 					     domain->iommu_did[iommu->seq_id],
 					     flags);
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 815c744e6a34..dc5020320323 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -625,9 +625,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 		}
 	}
 
-	if (flags & PASID_FLAG_PAGE_SNOOP)
-		pasid_set_pgsnp(pte);
-
 	pasid_set_domain_id(pte, did);
 	pasid_set_address_width(pte, iommu->agaw);
 	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
@@ -710,9 +707,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
 	pasid_set_fault_enable(pte);
 	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
 
-	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
-		pasid_set_pgsnp(pte);
-
 	/*
 	 * Since it is a second level only translation setup, we should
 	 * set SRE bit as well (addresses are expected to be GPAs).
-- 
2.25.1

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, Jason Gunthorpe <jgg@nvidia.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Kevin Tian <kevin.tian@intel.com>
Cc: Jacob jun Pan <jacob.jun.pan@intel.com>,
	Liu Yi L <yi.l.liu@intel.com>,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	Lu Baolu <baolu.lu@linux.intel.com>
Subject: [PATCH 5/5] iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
Date: Sun,  1 May 2022 19:24:34 +0800	[thread overview]
Message-ID: <20220501112434.874236-6-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20220501112434.874236-1-baolu.lu@linux.intel.com>

As enforce_cache_coherency has been introduced into the iommu_domain_ops,
the kernel component which owns the iommu domain is able to opt-in its
requirement for force snooping support. The iommu driver has no need to
hard code the page snoop control bit in the PASID table entries anymore.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/pasid.h | 1 -
 drivers/iommu/intel/iommu.c | 3 ---
 drivers/iommu/intel/pasid.c | 6 ------
 3 files changed, 10 deletions(-)

diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 583ea67fc783..394e6284ce1f 100644
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -48,7 +48,6 @@
  */
 #define PASID_FLAG_SUPERVISOR_MODE	BIT(0)
 #define PASID_FLAG_NESTED		BIT(1)
-#define PASID_FLAG_PAGE_SNOOP		BIT(2)
 
 /*
  * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index d5808495eb64..edd3d940eb25 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2432,9 +2432,6 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
 	if (level == 5)
 		flags |= PASID_FLAG_FL5LP;
 
-	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
-		flags |= PASID_FLAG_PAGE_SNOOP;
-
 	return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
 					     domain->iommu_did[iommu->seq_id],
 					     flags);
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 815c744e6a34..dc5020320323 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -625,9 +625,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 		}
 	}
 
-	if (flags & PASID_FLAG_PAGE_SNOOP)
-		pasid_set_pgsnp(pte);
-
 	pasid_set_domain_id(pte, did);
 	pasid_set_address_width(pte, iommu->agaw);
 	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
@@ -710,9 +707,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
 	pasid_set_fault_enable(pte);
 	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
 
-	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
-		pasid_set_pgsnp(pte);
-
 	/*
 	 * Since it is a second level only translation setup, we should
 	 * set SRE bit as well (addresses are expected to be GPAs).
-- 
2.25.1


  parent reply	other threads:[~2022-05-01 11:28 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-01 11:24 [PATCH 0/5] iommu/vt-d: Force snooping improvement Lu Baolu
2022-05-01 11:24 ` Lu Baolu
2022-05-01 11:24 ` [PATCH 1/5] iommu/vt-d: Block force-snoop domain attaching if no SC support Lu Baolu
2022-05-01 11:24   ` Lu Baolu
2022-05-02 13:04   ` Jason Gunthorpe via iommu
2022-05-02 13:04     ` Jason Gunthorpe
2022-05-01 11:24 ` [PATCH 2/5] iommu/vt-d: Set SNP bit only in second-level page table entries Lu Baolu
2022-05-01 11:24   ` Lu Baolu
2022-05-02 13:05   ` Jason Gunthorpe via iommu
2022-05-02 13:05     ` Jason Gunthorpe
2022-05-04  7:25     ` Baolu Lu
2022-05-04  7:25       ` Baolu Lu
2022-05-04 13:31       ` Jason Gunthorpe via iommu
2022-05-04 13:31         ` Jason Gunthorpe
2022-05-04 14:37         ` Baolu Lu
2022-05-04 14:37           ` Baolu Lu
2022-05-01 11:24 ` [PATCH 3/5] iommu/vt-d: Check domain force_snooping against attached devices Lu Baolu
2022-05-01 11:24   ` Lu Baolu
2022-05-02 13:17   ` Jason Gunthorpe via iommu
2022-05-02 13:17     ` Jason Gunthorpe
2022-05-04  7:58     ` Baolu Lu
2022-05-04  7:58       ` Baolu Lu
2022-05-02 21:31   ` Jacob Pan
2022-05-02 21:31     ` Jacob Pan
2022-05-04  8:06     ` Baolu Lu
2022-05-04  8:06       ` Baolu Lu
2022-05-01 11:24 ` [PATCH 4/5] iommu/vt-d: Remove domain_update_iommu_snooping() Lu Baolu
2022-05-01 11:24   ` Lu Baolu
2022-05-02 13:19   ` Jason Gunthorpe via iommu
2022-05-02 13:19     ` Jason Gunthorpe
2022-05-02 21:36   ` Jacob Pan
2022-05-02 21:36     ` Jacob Pan
2022-05-04  8:47     ` Baolu Lu
2022-05-04  8:47       ` Baolu Lu
2022-05-01 11:24 ` Lu Baolu [this message]
2022-05-01 11:24   ` [PATCH 5/5] iommu/vt-d: Remove hard coding PGSNP bit in PASID entries Lu Baolu
2022-05-02 13:19   ` Jason Gunthorpe via iommu
2022-05-02 13:19     ` Jason Gunthorpe
2022-05-04  8:49     ` Baolu Lu
2022-05-04  8:49       ` Baolu Lu

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