* [PATCH 0/2] mailbox: imx: support RST channel @ 2022-05-17 7:35 ` Peng Fan (OSS) 0 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> To i.MX generic MU, when linux stop remote core, the MU-B side is not reset because of hardware design, so MU-B contains valid configuration when remote core stops. Then when linux start remote core again, linux may notify remote core before remote core is ready for incoming message. So we need make sure MU is in reset state before remote core start. So add a RST channel which is only to reset MU when shutdown the RST mbox channel. Peng Fan (2): dt-bindings: mailbox: imx-mu: add RST channel mailbox: imx: support RST channel .../devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++-- drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++---- 2 files changed, 27 insertions(+), 8 deletions(-) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 0/2] mailbox: imx: support RST channel @ 2022-05-17 7:35 ` Peng Fan (OSS) 0 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> To i.MX generic MU, when linux stop remote core, the MU-B side is not reset because of hardware design, so MU-B contains valid configuration when remote core stops. Then when linux start remote core again, linux may notify remote core before remote core is ready for incoming message. So we need make sure MU is in reset state before remote core start. So add a RST channel which is only to reset MU when shutdown the RST mbox channel. Peng Fan (2): dt-bindings: mailbox: imx-mu: add RST channel mailbox: imx: support RST channel .../devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++-- drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++---- 2 files changed, 27 insertions(+), 8 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: mailbox: imx-mu: add RST channel 2022-05-17 7:35 ` Peng Fan (OSS) @ 2022-05-17 7:35 ` Peng Fan (OSS) -1 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> i.MX MU has a MUR bit which is to reset both the Processor B and the Processor A sides of the MU module, forcing all control and status registers to return to their default values (except the BHR bit in the ACR register and BHRM bit in BCR register), and all internal states to be cleared. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 7a86e7926dd2..191c1ce15009 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -72,14 +72,16 @@ properties: type : Channel type channel : Channel number - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are + This MU support 5 type of unidirectional channels, each type + has 4 channels except RST channel which only has 1 channel. + A total of 17 channels. Following types are supported: 0 - TX channel with 32bit transmit register and IRQ transmit acknowledgment support. 1 - RX channel with 32bit receive register and IRQ support 2 - TX doorbell channel. Without own register and no ACK support. 3 - RX doorbell channel. + 4 - RST channel const: 2 clocks: -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: mailbox: imx-mu: add RST channel @ 2022-05-17 7:35 ` Peng Fan (OSS) 0 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> i.MX MU has a MUR bit which is to reset both the Processor B and the Processor A sides of the MU module, forcing all control and status registers to return to their default values (except the BHR bit in the ACR register and BHRM bit in BCR register), and all internal states to be cleared. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 7a86e7926dd2..191c1ce15009 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -72,14 +72,16 @@ properties: type : Channel type channel : Channel number - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are + This MU support 5 type of unidirectional channels, each type + has 4 channels except RST channel which only has 1 channel. + A total of 17 channels. Following types are supported: 0 - TX channel with 32bit transmit register and IRQ transmit acknowledgment support. 1 - RX channel with 32bit receive register and IRQ support 2 - TX doorbell channel. Without own register and no ACK support. 3 - RX doorbell channel. + 4 - RST channel const: 2 clocks: -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: imx-mu: add RST channel 2022-05-17 7:35 ` Peng Fan (OSS) @ 2022-05-18 1:19 ` Rob Herring -1 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-05-18 1:19 UTC (permalink / raw) To: Peng Fan (OSS) Cc: devicetree, linux-kernel, linux-imx, shawnguo, Peng Fan, linux-arm-kernel, kernel, festevam, robh+dt, krzysztof.kozlowski+dt, s.hauer On Tue, 17 May 2022 15:35:17 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX MU has a MUR bit which is to reset both the Processor B and the > Processor A sides of the MU module, forcing all control and status > registers to return to their default values (except the BHR bit in the ACR > register and BHRM bit in BCR register), and all internal states to be > cleared. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: imx-mu: add RST channel @ 2022-05-18 1:19 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-05-18 1:19 UTC (permalink / raw) To: Peng Fan (OSS) Cc: devicetree, linux-kernel, linux-imx, shawnguo, Peng Fan, linux-arm-kernel, kernel, festevam, robh+dt, krzysztof.kozlowski+dt, s.hauer On Tue, 17 May 2022 15:35:17 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX MU has a MUR bit which is to reset both the Processor B and the > Processor A sides of the MU module, forcing all control and status > registers to return to their default values (except the BHR bit in the ACR > register and BHRM bit in BCR register), and all internal states to be > cleared. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] mailbox: imx: support RST channel 2022-05-17 7:35 ` Peng Fan (OSS) @ 2022-05-17 7:35 ` Peng Fan (OSS) -1 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> i.MX generic MU supports MU-A/B reset feature. When stop/start remotecore, MU is not reset. So when Linux stop remotecore, the MU-B side BCR may contain valid configuration, because MU-B is not reset. So when linux start Mcore again and notify Mcore, Mcore is not ready to handle MU interrupt and cause issues. So need reset MU when stop Mcore. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index e88f544a1548..ce05ddc8402c 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -19,7 +19,7 @@ #include <linux/suspend.h> #include <linux/slab.h> -#define IMX_MU_CHANS 16 +#define IMX_MU_CHANS 17 /* TX0/RX0/RXDB[0-3] */ #define IMX_MU_SCU_CHANS 6 /* TX0/RX0 */ @@ -35,9 +35,11 @@ enum imx_mu_chan_type { IMX_MU_TYPE_RX = 1, /* Rx */ IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ + IMX_MU_TYPE_RST = 4, /* Reset */ }; enum imx_mu_xcr { + IMX_MU_CR, IMX_MU_GIER, IMX_MU_GCR, IMX_MU_TCR, @@ -50,6 +52,7 @@ enum imx_mu_xsr { IMX_MU_GSR, IMX_MU_TSR, IMX_MU_RSR, + IMX_MU_xSR_MAX, }; struct imx_sc_rpc_msg_max { @@ -85,7 +88,7 @@ struct imx_mu_priv { int irq[IMX_MU_CHANS]; bool suspend; - u32 xcr[4]; + u32 xcr[IMX_MU_xCR_MAX]; bool side_b; }; @@ -105,8 +108,8 @@ struct imx_mu_dcfg { enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ u32 xRR; /* Receive Register0 */ - u32 xSR[4]; /* Status Registers */ - u32 xCR[4]; /* Control Registers */ + u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ + u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ }; #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) @@ -121,6 +124,9 @@ struct imx_mu_dcfg { #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) /* General Purpose Interrupt Request */ #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) +/* MU reset */ +#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) +#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) @@ -497,6 +503,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + return IRQ_NONE; default: dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", cp->type); @@ -581,6 +589,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) { struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; + int ret; + u32 sr; if (cp->type == IMX_MU_TYPE_TXDB) { tasklet_kill(&cp->txdb_tasklet); @@ -598,6 +608,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan) case IMX_MU_TYPE_RXDB: imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); + ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, + !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); + if (ret) + dev_warn(priv->dev, "RST channel timeout\n"); + break; default: break; } @@ -867,7 +884,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { .xTR = 0x0, .xRR = 0x10, .xSR = {0x20, 0x20, 0x20, 0x20}, - .xCR = {0x24, 0x24, 0x24, 0x24}, + .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { @@ -891,7 +908,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .xTR = 0x200, .xRR = 0x280, .xSR = {0xC, 0x118, 0x124, 0x12C}, - .xCR = {0x110, 0x114, 0x120, 0x128}, + .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] mailbox: imx: support RST channel @ 2022-05-17 7:35 ` Peng Fan (OSS) 0 siblings, 0 replies; 8+ messages in thread From: Peng Fan (OSS) @ 2022-05-17 7:35 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer Cc: kernel, festevam, linux-imx, devicetree, linux-kernel, linux-arm-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> i.MX generic MU supports MU-A/B reset feature. When stop/start remotecore, MU is not reset. So when Linux stop remotecore, the MU-B side BCR may contain valid configuration, because MU-B is not reset. So when linux start Mcore again and notify Mcore, Mcore is not ready to handle MU interrupt and cause issues. So need reset MU when stop Mcore. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index e88f544a1548..ce05ddc8402c 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -19,7 +19,7 @@ #include <linux/suspend.h> #include <linux/slab.h> -#define IMX_MU_CHANS 16 +#define IMX_MU_CHANS 17 /* TX0/RX0/RXDB[0-3] */ #define IMX_MU_SCU_CHANS 6 /* TX0/RX0 */ @@ -35,9 +35,11 @@ enum imx_mu_chan_type { IMX_MU_TYPE_RX = 1, /* Rx */ IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ + IMX_MU_TYPE_RST = 4, /* Reset */ }; enum imx_mu_xcr { + IMX_MU_CR, IMX_MU_GIER, IMX_MU_GCR, IMX_MU_TCR, @@ -50,6 +52,7 @@ enum imx_mu_xsr { IMX_MU_GSR, IMX_MU_TSR, IMX_MU_RSR, + IMX_MU_xSR_MAX, }; struct imx_sc_rpc_msg_max { @@ -85,7 +88,7 @@ struct imx_mu_priv { int irq[IMX_MU_CHANS]; bool suspend; - u32 xcr[4]; + u32 xcr[IMX_MU_xCR_MAX]; bool side_b; }; @@ -105,8 +108,8 @@ struct imx_mu_dcfg { enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ u32 xRR; /* Receive Register0 */ - u32 xSR[4]; /* Status Registers */ - u32 xCR[4]; /* Control Registers */ + u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ + u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ }; #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) @@ -121,6 +124,9 @@ struct imx_mu_dcfg { #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) /* General Purpose Interrupt Request */ #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) +/* MU reset */ +#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) +#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) @@ -497,6 +503,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + return IRQ_NONE; default: dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", cp->type); @@ -581,6 +589,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) { struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; + int ret; + u32 sr; if (cp->type == IMX_MU_TYPE_TXDB) { tasklet_kill(&cp->txdb_tasklet); @@ -598,6 +608,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan) case IMX_MU_TYPE_RXDB: imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); + ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, + !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); + if (ret) + dev_warn(priv->dev, "RST channel timeout\n"); + break; default: break; } @@ -867,7 +884,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { .xTR = 0x0, .xRR = 0x10, .xSR = {0x20, 0x20, 0x20, 0x20}, - .xCR = {0x24, 0x24, 0x24, 0x24}, + .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { @@ -891,7 +908,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .xTR = 0x200, .xRR = 0x280, .xSR = {0xC, 0x118, 0x124, 0x12C}, - .xCR = {0x110, 0x114, 0x120, 0x128}, + .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-05-18 1:20 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-05-17 7:35 [PATCH 0/2] mailbox: imx: support RST channel Peng Fan (OSS) 2022-05-17 7:35 ` Peng Fan (OSS) 2022-05-17 7:35 ` [PATCH 1/2] dt-bindings: mailbox: imx-mu: add " Peng Fan (OSS) 2022-05-17 7:35 ` Peng Fan (OSS) 2022-05-18 1:19 ` Rob Herring 2022-05-18 1:19 ` Rob Herring 2022-05-17 7:35 ` [PATCH 2/2] mailbox: imx: support " Peng Fan (OSS) 2022-05-17 7:35 ` Peng Fan (OSS)
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.