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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v2 2/6] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx
Date: Fri, 20 May 2022 17:16:34 +0100	[thread overview]
Message-ID: <20220520161639.324236-3-broonie@kernel.org> (raw)
In-Reply-To: <20220520161639.324236-1-broonie@kernel.org>

Convert the various CONTEXTIDR_ELx register definitions to be automatically
generated following the definitions in DDI0487H.a. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/sysreg.h |  2 --
 arch/arm64/tools/sysreg         | 17 +++++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0cea8bdb792f..4fd64e6ec407 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -449,7 +449,6 @@
 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
 
-#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
 #define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
 
 #define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
@@ -629,7 +628,6 @@
 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
-#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 0067d07f9125..b2e01e108b8e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -212,6 +212,15 @@ Sysreg	SMCR_EL1	3	0	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+SysregFields	CONTEXTIDR_ELx
+Res0	63:32
+Field	31:0	PROCID
+EndSysregFields
+
+Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
 Sysreg	CLIDR_EL1	3	1	0	0	1
 Res0	63:47
 Field	46:33	Ttypen
@@ -270,6 +279,10 @@ Sysreg	SMCR_EL2	3	4	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	CONTEXTIDR_EL2	3	4	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
 Sysreg	ZCR_EL12	3	5	1	2	0
 Fields	ZCR_ELx
 EndSysreg
@@ -278,6 +291,10 @@ Sysreg	SMCR_EL12	3	5	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field	63:48	ASID
 Field	47:1	BADDR
-- 
2.30.2


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  parent reply	other threads:[~2022-05-20 16:20 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 16:16 [PATCH v2 0/6] arm64/sysreg: More system register generation Mark Brown
2022-05-20 16:16 ` [PATCH v2 1/6] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
2022-05-20 16:16 ` Mark Brown [this message]
2022-05-20 16:16 ` [PATCH v2 3/6] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
2022-05-20 16:30   ` Mark Rutland
2022-05-20 16:16 ` [PATCH v2 4/6] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
2022-05-20 16:16 ` [PATCH v2 5/6] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
2022-05-20 16:16 ` [PATCH v2 6/6] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
2022-05-20 17:56 ` [PATCH v2 0/6] arm64/sysreg: More system register generation Catalin Marinas

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