* [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) hardware which used as optimization of opp voltage table for corresponding dvfs drivers. This series is based on Roger's series [1]. [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com Change since v2: - Reuse platform probe of MT8192 for MT8195. - Remove unnecessary svs bank parameters of MT8195. - Remove sw id check for MT8195 efuse parsing. Change since v1: - Add myself as a co-maintainer of mtk-svs.yaml. - Fix MT8186 error handling in platform probe. - Add dt-bindings and support for MT8195 platform. Jia-Wei Chang (4): dt-bindings: soc: mediatek: add mt8186 svs dt-bindings soc: mediatek: svs: add support for mt8186 dt-bindings: soc: mediatek: add mt8195 svs dt-bindings soc: mediatek: svs: add support for mt8195 .../bindings/soc/mediatek/mtk-svs.yaml | 3 + drivers/soc/mediatek/mtk-svs.c | 502 +++++++++++++++++- 2 files changed, 498 insertions(+), 7 deletions(-) -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) hardware which used as optimization of opp voltage table for corresponding dvfs drivers. This series is based on Roger's series [1]. [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com Change since v2: - Reuse platform probe of MT8192 for MT8195. - Remove unnecessary svs bank parameters of MT8195. - Remove sw id check for MT8195 efuse parsing. Change since v1: - Add myself as a co-maintainer of mtk-svs.yaml. - Fix MT8186 error handling in platform probe. - Add dt-bindings and support for MT8195 platform. Jia-Wei Chang (4): dt-bindings: soc: mediatek: add mt8186 svs dt-bindings soc: mediatek: svs: add support for mt8186 dt-bindings: soc: mediatek: add mt8195 svs dt-bindings soc: mediatek: svs: add support for mt8195 .../bindings/soc/mediatek/mtk-svs.yaml | 3 + drivers/soc/mediatek/mtk-svs.c | 502 +++++++++++++++++- 2 files changed, 498 insertions(+), 7 deletions(-) -- 2.18.0 ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) hardware which used as optimization of opp voltage table for corresponding dvfs drivers. This series is based on Roger's series [1]. [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com Change since v2: - Reuse platform probe of MT8192 for MT8195. - Remove unnecessary svs bank parameters of MT8195. - Remove sw id check for MT8195 efuse parsing. Change since v1: - Add myself as a co-maintainer of mtk-svs.yaml. - Fix MT8186 error handling in platform probe. - Add dt-bindings and support for MT8195 platform. Jia-Wei Chang (4): dt-bindings: soc: mediatek: add mt8186 svs dt-bindings soc: mediatek: svs: add support for mt8186 dt-bindings: soc: mediatek: add mt8195 svs dt-bindings soc: mediatek: svs: add support for mt8195 .../bindings/soc/mediatek/mtk-svs.yaml | 3 + drivers/soc/mediatek/mtk-svs.c | 502 +++++++++++++++++- 2 files changed, 498 insertions(+), 7 deletions(-) -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 8:40 ` Tim Chang -1 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8186 svs compatible in dt-bindings and add myself as a co-maintainer. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index d911fa2d40ef..c86a5430641f 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -10,6 +10,7 @@ maintainers: - Roger Lu <roger.lu@mediatek.com> - Matthias Brugger <matthias.bgg@gmail.com> - Kevin Hilman <khilman@kernel.org> + - Jia-Wei Chang <jia-wei.chang@mediatek.com> description: |+ The SVS engine is a piece of hardware which has several @@ -22,6 +23,7 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8192-svs reg: -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8186 svs compatible in dt-bindings and add myself as a co-maintainer. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index d911fa2d40ef..c86a5430641f 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -10,6 +10,7 @@ maintainers: - Roger Lu <roger.lu@mediatek.com> - Matthias Brugger <matthias.bgg@gmail.com> - Kevin Hilman <khilman@kernel.org> + - Jia-Wei Chang <jia-wei.chang@mediatek.com> description: |+ The SVS engine is a piece of hardware which has several @@ -22,6 +23,7 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8192-svs reg: -- 2.18.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8186 svs compatible in dt-bindings and add myself as a co-maintainer. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index d911fa2d40ef..c86a5430641f 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -10,6 +10,7 @@ maintainers: - Roger Lu <roger.lu@mediatek.com> - Matthias Brugger <matthias.bgg@gmail.com> - Kevin Hilman <khilman@kernel.org> + - Jia-Wei Chang <jia-wei.chang@mediatek.com> description: |+ The SVS engine is a piece of hardware which has several @@ -22,6 +23,7 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8192-svs reg: -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-24 2:05 ` Rob Herring -1 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2022-05-24 2:05 UTC (permalink / raw) To: Tim Chang Cc: linux-arm-kernel, linux-mediatek, Roger Lu, AngeloGioacchino Del Regno, Rob Herring, hsinyi, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Krzysztof Kozlowski, devicetree, Philipp Zabel, linux-kernel, Kevin Hilman On Mon, 23 May 2022 16:40:31 +0800, Tim Chang wrote: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Add mt8186 svs compatible in dt-bindings and add myself as a > co-maintainer. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings @ 2022-05-24 2:05 ` Rob Herring 0 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2022-05-24 2:05 UTC (permalink / raw) To: Tim Chang Cc: linux-arm-kernel, linux-mediatek, Roger Lu, AngeloGioacchino Del Regno, Rob Herring, hsinyi, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Krzysztof Kozlowski, devicetree, Philipp Zabel, linux-kernel, Kevin Hilman On Mon, 23 May 2022 16:40:31 +0800, Tim Chang wrote: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Add mt8186 svs compatible in dt-bindings and add myself as a > co-maintainer. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings @ 2022-05-24 2:05 ` Rob Herring 0 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2022-05-24 2:05 UTC (permalink / raw) To: Tim Chang Cc: linux-arm-kernel, linux-mediatek, Roger Lu, AngeloGioacchino Del Regno, Rob Herring, hsinyi, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Krzysztof Kozlowski, devicetree, Philipp Zabel, linux-kernel, Kevin Hilman On Mon, 23 May 2022 16:40:31 +0800, Tim Chang wrote: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Add mt8186 svs compatible in dt-bindings and add myself as a > co-maintainer. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 8:40 ` Tim Chang -1 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- 1 file changed, 344 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 606a00a2e57d..656d0361ff7d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -355,6 +355,7 @@ struct svs_platform_data { * @dcbdet: svs efuse data * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank + * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank * * Svs bank will generate suitalbe voltages by below general math equation @@ -417,6 +418,7 @@ struct svs_bank { u32 dcbdet; u32 dcmdet; u32 turn_pt; + u32 vbin_turn_pt; u32 type; }; @@ -692,11 +694,12 @@ static int svs_status_debug_show(struct seq_file *m, void *v) ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret) - seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", - svsb->name, svsb->turn_pt); + seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); else - seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", - svsb->name, tzone_temp, svsb->turn_pt); + seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, tzone_temp, svsb->vbin_turn_pt, + svsb->turn_pt); for (i = 0; i < svsb->opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, @@ -889,9 +892,11 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) opp_stop = svsb->opp_count; } - for (i = opp_start; i < opp_stop; i++) + for (i = opp_start; i < opp_stop; i++) { if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) svsb->volt[i] -= svsb->dvt_fixed; + svsb->volt[i] += svsb->volt_od; + } } static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) @@ -982,6 +987,10 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) struct svs_bank *svsb = svsp->pbank; u32 temp, i; + if (svsb->phase == SVSB_PHASE_MON && + svsb->volt_flags & SVSB_MON_VOLT_IGNORE) + return; + temp = svs_readl_relaxed(svsp, VOP74); svsb->volt[14] = (temp >> 24) & GENMASK(7, 0); svsb->volt[12] = (temp >> 16) & GENMASK(7, 0); @@ -1007,8 +1016,34 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) svsb->volt[14], svsb->freq_pct[15]); - for (i = 0; i < svsb->opp_count; i++) + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) + svsb->volt[i] -= svsb->dvt_fixed; svsb->volt[i] += svsb->volt_od; + } + + /* For voltage bin support */ + if (svsb->opp_dfreq[0] > svsb->freq_base) { + svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], + svsb->volt_step, + svsb->volt_base); + + /* Find voltage bin turn point */ + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->opp_dfreq[i] <= svsb->freq_base) { + svsb->vbin_turn_pt = i; + break; + } + } + + /* Override svs bank voltages */ + for (i = 1; i < svsb->vbin_turn_pt; i++) + svsb->volt[i] = interpolate(svsb->freq_pct[0], + svsb->freq_pct[svsb->vbin_turn_pt], + svsb->volt[0], + svsb->volt[svsb->vbin_turn_pt], + svsb->freq_pct[i]); + } } static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) @@ -1556,7 +1591,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) svsb->name = "SVSB_CPU_LITTLE"; break; case SVSB_CPU_BIG: - svsb->name = "SVSB_CPU_BIG"; + if (svsb->type == SVSB_HIGH) + svsb->name = "SVSB_CPU_BIG_HIGH"; + else if (svsb->type == SVSB_LOW) + svsb->name = "SVSB_CPU_BIG_LOW"; + else + svsb->name = "SVSB_CPU_BIG"; break; case SVSB_CCI: svsb->name = "SVSB_CCI"; @@ -1719,6 +1759,103 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) return true; } +static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[0]) { + dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_BIG: + if (svsb->type == SVSB_HIGH) { + svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); + } else if (svsb->type == SVSB_LOW) { + svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); + } + break; + case SVSB_CPU_LITTLE: + svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); + break; + case SVSB_CCI: + svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); + break; + case SVSB_GPU: + svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return false; + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (!golden_temp) + golden_temp = 50; + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 409; + svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2037,6 +2174,50 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) return 0; } +static int svs_mt8186_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev = svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_LITTLE: + case SVSB_CPU_BIG: + svsb->opp_dev = get_cpu_device(svsb->cpu_id); + break; + case SVSB_CCI: + svsb->opp_dev = svs_add_device_link(svsp, "cci"); + break; + case SVSB_GPU: + svsb->opp_dev = svs_add_device_link(svsp, "mali"); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return -EINVAL; + } + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2131,6 +2312,149 @@ static struct svs_bank svs_mt8192_banks[] = { }, }; +static struct svs_bank svs_mt8186_banks[] = { + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1670000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x59, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x3, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .tzone_name = "cpu_big0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2050000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x73, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2000000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0102, + .int_st = BIT(2), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1400000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0103, + .int_st = BIT(3), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "mfg", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 850000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x58, + .vmin = 0x20, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x4, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0104, + .int_st = BIT(4), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] = { { .sw_id = SVSB_CPU_LITTLE, @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .bank_max = ARRAY_SIZE(svs_mt8192_banks), }; +static const struct svs_platform_data svs_mt8186_platform_data = { + .name = "mt8186-svs", + .banks = svs_mt8186_banks, + .efuse_parsing = svs_mt8186_efuse_parsing, + .probe = svs_mt8186_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8186_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data = { .name = "mt8183-svs", .banks = svs_mt8183_banks, @@ -2259,6 +2593,9 @@ static const struct of_device_id svs_of_match[] = { { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, + }, { + .compatible = "mediatek,mt8186-svs", + .data = &svs_mt8186_platform_data, }, { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data, -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- 1 file changed, 344 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 606a00a2e57d..656d0361ff7d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -355,6 +355,7 @@ struct svs_platform_data { * @dcbdet: svs efuse data * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank + * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank * * Svs bank will generate suitalbe voltages by below general math equation @@ -417,6 +418,7 @@ struct svs_bank { u32 dcbdet; u32 dcmdet; u32 turn_pt; + u32 vbin_turn_pt; u32 type; }; @@ -692,11 +694,12 @@ static int svs_status_debug_show(struct seq_file *m, void *v) ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret) - seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", - svsb->name, svsb->turn_pt); + seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); else - seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", - svsb->name, tzone_temp, svsb->turn_pt); + seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, tzone_temp, svsb->vbin_turn_pt, + svsb->turn_pt); for (i = 0; i < svsb->opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, @@ -889,9 +892,11 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) opp_stop = svsb->opp_count; } - for (i = opp_start; i < opp_stop; i++) + for (i = opp_start; i < opp_stop; i++) { if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) svsb->volt[i] -= svsb->dvt_fixed; + svsb->volt[i] += svsb->volt_od; + } } static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) @@ -982,6 +987,10 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) struct svs_bank *svsb = svsp->pbank; u32 temp, i; + if (svsb->phase == SVSB_PHASE_MON && + svsb->volt_flags & SVSB_MON_VOLT_IGNORE) + return; + temp = svs_readl_relaxed(svsp, VOP74); svsb->volt[14] = (temp >> 24) & GENMASK(7, 0); svsb->volt[12] = (temp >> 16) & GENMASK(7, 0); @@ -1007,8 +1016,34 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) svsb->volt[14], svsb->freq_pct[15]); - for (i = 0; i < svsb->opp_count; i++) + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) + svsb->volt[i] -= svsb->dvt_fixed; svsb->volt[i] += svsb->volt_od; + } + + /* For voltage bin support */ + if (svsb->opp_dfreq[0] > svsb->freq_base) { + svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], + svsb->volt_step, + svsb->volt_base); + + /* Find voltage bin turn point */ + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->opp_dfreq[i] <= svsb->freq_base) { + svsb->vbin_turn_pt = i; + break; + } + } + + /* Override svs bank voltages */ + for (i = 1; i < svsb->vbin_turn_pt; i++) + svsb->volt[i] = interpolate(svsb->freq_pct[0], + svsb->freq_pct[svsb->vbin_turn_pt], + svsb->volt[0], + svsb->volt[svsb->vbin_turn_pt], + svsb->freq_pct[i]); + } } static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) @@ -1556,7 +1591,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) svsb->name = "SVSB_CPU_LITTLE"; break; case SVSB_CPU_BIG: - svsb->name = "SVSB_CPU_BIG"; + if (svsb->type == SVSB_HIGH) + svsb->name = "SVSB_CPU_BIG_HIGH"; + else if (svsb->type == SVSB_LOW) + svsb->name = "SVSB_CPU_BIG_LOW"; + else + svsb->name = "SVSB_CPU_BIG"; break; case SVSB_CCI: svsb->name = "SVSB_CCI"; @@ -1719,6 +1759,103 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) return true; } +static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[0]) { + dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_BIG: + if (svsb->type == SVSB_HIGH) { + svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); + } else if (svsb->type == SVSB_LOW) { + svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); + } + break; + case SVSB_CPU_LITTLE: + svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); + break; + case SVSB_CCI: + svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); + break; + case SVSB_GPU: + svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return false; + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (!golden_temp) + golden_temp = 50; + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 409; + svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2037,6 +2174,50 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) return 0; } +static int svs_mt8186_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev = svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_LITTLE: + case SVSB_CPU_BIG: + svsb->opp_dev = get_cpu_device(svsb->cpu_id); + break; + case SVSB_CCI: + svsb->opp_dev = svs_add_device_link(svsp, "cci"); + break; + case SVSB_GPU: + svsb->opp_dev = svs_add_device_link(svsp, "mali"); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return -EINVAL; + } + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2131,6 +2312,149 @@ static struct svs_bank svs_mt8192_banks[] = { }, }; +static struct svs_bank svs_mt8186_banks[] = { + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1670000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x59, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x3, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .tzone_name = "cpu_big0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2050000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x73, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2000000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0102, + .int_st = BIT(2), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1400000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0103, + .int_st = BIT(3), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "mfg", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 850000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x58, + .vmin = 0x20, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x4, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0104, + .int_st = BIT(4), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] = { { .sw_id = SVSB_CPU_LITTLE, @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .bank_max = ARRAY_SIZE(svs_mt8192_banks), }; +static const struct svs_platform_data svs_mt8186_platform_data = { + .name = "mt8186-svs", + .banks = svs_mt8186_banks, + .efuse_parsing = svs_mt8186_efuse_parsing, + .probe = svs_mt8186_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8186_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data = { .name = "mt8183-svs", .banks = svs_mt8183_banks, @@ -2259,6 +2593,9 @@ static const struct of_device_id svs_of_match[] = { { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, + }, { + .compatible = "mediatek,mt8186-svs", + .data = &svs_mt8186_platform_data, }, { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data, -- 2.18.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- 1 file changed, 344 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 606a00a2e57d..656d0361ff7d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -355,6 +355,7 @@ struct svs_platform_data { * @dcbdet: svs efuse data * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank + * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank * * Svs bank will generate suitalbe voltages by below general math equation @@ -417,6 +418,7 @@ struct svs_bank { u32 dcbdet; u32 dcmdet; u32 turn_pt; + u32 vbin_turn_pt; u32 type; }; @@ -692,11 +694,12 @@ static int svs_status_debug_show(struct seq_file *m, void *v) ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret) - seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", - svsb->name, svsb->turn_pt); + seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); else - seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", - svsb->name, tzone_temp, svsb->turn_pt); + seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n", + svsb->name, tzone_temp, svsb->vbin_turn_pt, + svsb->turn_pt); for (i = 0; i < svsb->opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, @@ -889,9 +892,11 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) opp_stop = svsb->opp_count; } - for (i = opp_start; i < opp_stop; i++) + for (i = opp_start; i < opp_stop; i++) { if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) svsb->volt[i] -= svsb->dvt_fixed; + svsb->volt[i] += svsb->volt_od; + } } static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) @@ -982,6 +987,10 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) struct svs_bank *svsb = svsp->pbank; u32 temp, i; + if (svsb->phase == SVSB_PHASE_MON && + svsb->volt_flags & SVSB_MON_VOLT_IGNORE) + return; + temp = svs_readl_relaxed(svsp, VOP74); svsb->volt[14] = (temp >> 24) & GENMASK(7, 0); svsb->volt[12] = (temp >> 16) & GENMASK(7, 0); @@ -1007,8 +1016,34 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) svsb->volt[14], svsb->freq_pct[15]); - for (i = 0; i < svsb->opp_count; i++) + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) + svsb->volt[i] -= svsb->dvt_fixed; svsb->volt[i] += svsb->volt_od; + } + + /* For voltage bin support */ + if (svsb->opp_dfreq[0] > svsb->freq_base) { + svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], + svsb->volt_step, + svsb->volt_base); + + /* Find voltage bin turn point */ + for (i = 0; i < svsb->opp_count; i++) { + if (svsb->opp_dfreq[i] <= svsb->freq_base) { + svsb->vbin_turn_pt = i; + break; + } + } + + /* Override svs bank voltages */ + for (i = 1; i < svsb->vbin_turn_pt; i++) + svsb->volt[i] = interpolate(svsb->freq_pct[0], + svsb->freq_pct[svsb->vbin_turn_pt], + svsb->volt[0], + svsb->volt[svsb->vbin_turn_pt], + svsb->freq_pct[i]); + } } static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) @@ -1556,7 +1591,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) svsb->name = "SVSB_CPU_LITTLE"; break; case SVSB_CPU_BIG: - svsb->name = "SVSB_CPU_BIG"; + if (svsb->type == SVSB_HIGH) + svsb->name = "SVSB_CPU_BIG_HIGH"; + else if (svsb->type == SVSB_LOW) + svsb->name = "SVSB_CPU_BIG_LOW"; + else + svsb->name = "SVSB_CPU_BIG"; break; case SVSB_CCI: svsb->name = "SVSB_CCI"; @@ -1719,6 +1759,103 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) return true; } +static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[0]) { + dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_BIG: + if (svsb->type == SVSB_HIGH) { + svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); + } else if (svsb->type == SVSB_LOW) { + svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); + } + break; + case SVSB_CPU_LITTLE: + svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); + break; + case SVSB_CCI: + svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); + break; + case SVSB_GPU: + svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); + svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0); + svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return false; + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (!golden_temp) + golden_temp = 50; + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 409; + svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2037,6 +2174,50 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) return 0; } +static int svs_mt8186_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev = svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_LITTLE: + case SVSB_CPU_BIG: + svsb->opp_dev = get_cpu_device(svsb->cpu_id); + break; + case SVSB_CCI: + svsb->opp_dev = svs_add_device_link(svsp, "cci"); + break; + case SVSB_GPU: + svsb->opp_dev = svs_add_device_link(svsp, "mali"); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return -EINVAL; + } + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2131,6 +2312,149 @@ static struct svs_bank svs_mt8192_banks[] = { }, }; +static struct svs_bank svs_mt8186_banks[] = { + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1670000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x59, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x3, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_CPU_BIG, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .tzone_name = "cpu_big0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2050000000, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 4, + .vmax = 0x73, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 2000000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0102, + .int_st = BIT(2), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "cpu_zone0", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 1400000000, + .volt_step = 6250, + .volt_base = 400000, + .volt_od = 3, + .vmax = 0x65, + .vmin = 0x20, + .age_config = 0x1, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0103, + .int_st = BIT(3), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + }, + { + .sw_id = SVSB_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "mfg", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 850000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x58, + .vmin = 0x20, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x4, + .vco = 0x10, + .chk_shift = 0x87, + .core_sel = 0x0fff0104, + .int_st = BIT(4), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] = { { .sw_id = SVSB_CPU_LITTLE, @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .bank_max = ARRAY_SIZE(svs_mt8192_banks), }; +static const struct svs_platform_data svs_mt8186_platform_data = { + .name = "mt8186-svs", + .banks = svs_mt8186_banks, + .efuse_parsing = svs_mt8186_efuse_parsing, + .probe = svs_mt8186_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8186_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data = { .name = "mt8183-svs", .banks = svs_mt8183_banks, @@ -2259,6 +2593,9 @@ static const struct of_device_id svs_of_match[] = { { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, + }, { + .compatible = "mediatek,mt8186-svs", + .data = &svs_mt8186_platform_data, }, { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data, -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno -1 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > MT8186 svs has a number of banks which used as optimization of opp > voltage table for corresponding dvfs drivers. > MT8186 svs big core uses 2-line high bank and low bank to optimize the > voltage of opp table for higher and lower frequency respectively. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- > 1 file changed, 344 insertions(+), 7 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 606a00a2e57d..656d0361ff7d 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c ..snip.. > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > }; > > +static const struct svs_platform_data svs_mt8186_platform_data = { > + .name = "mt8186-svs", > + .banks = svs_mt8186_banks, > + .efuse_parsing = svs_mt8186_efuse_parsing, > + .probe = svs_mt8186_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, I know I gave you my R-b tag earlier, but I've just noticed that: please remove irqflags, as this kind of flags are specified in devicetree and it is not necessary to specify them here. Thanks, Angelo _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > MT8186 svs has a number of banks which used as optimization of opp > voltage table for corresponding dvfs drivers. > MT8186 svs big core uses 2-line high bank and low bank to optimize the > voltage of opp table for higher and lower frequency respectively. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- > 1 file changed, 344 insertions(+), 7 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 606a00a2e57d..656d0361ff7d 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c ..snip.. > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > }; > > +static const struct svs_platform_data svs_mt8186_platform_data = { > + .name = "mt8186-svs", > + .banks = svs_mt8186_banks, > + .efuse_parsing = svs_mt8186_efuse_parsing, > + .probe = svs_mt8186_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, I know I gave you my R-b tag earlier, but I've just noticed that: please remove irqflags, as this kind of flags are specified in devicetree and it is not necessary to specify them here. Thanks, Angelo ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > MT8186 svs has a number of banks which used as optimization of opp > voltage table for corresponding dvfs drivers. > MT8186 svs big core uses 2-line high bank and low bank to optimize the > voltage of opp table for higher and lower frequency respectively. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- > 1 file changed, 344 insertions(+), 7 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 606a00a2e57d..656d0361ff7d 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c ..snip.. > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_platform_data = { > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > }; > > +static const struct svs_platform_data svs_mt8186_platform_data = { > + .name = "mt8186-svs", > + .banks = svs_mt8186_banks, > + .efuse_parsing = svs_mt8186_efuse_parsing, > + .probe = svs_mt8186_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, I know I gave you my R-b tag earlier, but I've just noticed that: please remove irqflags, as this kind of flags are specified in devicetree and it is not necessary to specify them here. Thanks, Angelo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 2022-05-23 9:38 ` AngeloGioacchino Del Regno (?) @ 2022-05-26 5:52 ` Jia-Wei Chang -1 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:52 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > MT8186 svs has a number of banks which used as optimization of opp > > voltage table for corresponding dvfs drivers. > > MT8186 svs big core uses 2-line high bank and low bank to optimize > > the > > voltage of opp table for higher and lower frequency respectively. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > drivers/soc/mediatek/mtk-svs.c | 351 > > ++++++++++++++++++++++++++++++++- > > 1 file changed, 344 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 606a00a2e57d..656d0361ff7d 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > ..snip.. > > > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data > > svs_mt8192_platform_data = { > > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > > }; > > > > +static const struct svs_platform_data svs_mt8186_platform_data = { > > + .name = "mt8186-svs", > > + .banks = svs_mt8186_banks, > > + .efuse_parsing = svs_mt8186_efuse_parsing, > > + .probe = svs_mt8186_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > I know I gave you my R-b tag earlier, but I've just noticed that: > please remove > irqflags, as this kind of flags are specified in devicetree and it is > not > necessary to specify them here. > > Thanks, > Angelo Hi Angelo, Sure, I will remove it in the next version. Thanks. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-26 5:52 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:52 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > MT8186 svs has a number of banks which used as optimization of opp > > voltage table for corresponding dvfs drivers. > > MT8186 svs big core uses 2-line high bank and low bank to optimize > > the > > voltage of opp table for higher and lower frequency respectively. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > drivers/soc/mediatek/mtk-svs.c | 351 > > ++++++++++++++++++++++++++++++++- > > 1 file changed, 344 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 606a00a2e57d..656d0361ff7d 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > ..snip.. > > > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data > > svs_mt8192_platform_data = { > > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > > }; > > > > +static const struct svs_platform_data svs_mt8186_platform_data = { > > + .name = "mt8186-svs", > > + .banks = svs_mt8186_banks, > > + .efuse_parsing = svs_mt8186_efuse_parsing, > > + .probe = svs_mt8186_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > I know I gave you my R-b tag earlier, but I've just noticed that: > please remove > irqflags, as this kind of flags are specified in devicetree and it is > not > necessary to specify them here. > > Thanks, > Angelo Hi Angelo, Sure, I will remove it in the next version. Thanks. ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 @ 2022-05-26 5:52 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:52 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > MT8186 svs has a number of banks which used as optimization of opp > > voltage table for corresponding dvfs drivers. > > MT8186 svs big core uses 2-line high bank and low bank to optimize > > the > > voltage of opp table for higher and lower frequency respectively. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > drivers/soc/mediatek/mtk-svs.c | 351 > > ++++++++++++++++++++++++++++++++- > > 1 file changed, 344 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 606a00a2e57d..656d0361ff7d 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > ..snip.. > > > @@ -2245,6 +2569,16 @@ static const struct svs_platform_data > > svs_mt8192_platform_data = { > > .bank_max = ARRAY_SIZE(svs_mt8192_banks), > > }; > > > > +static const struct svs_platform_data svs_mt8186_platform_data = { > > + .name = "mt8186-svs", > > + .banks = svs_mt8186_banks, > > + .efuse_parsing = svs_mt8186_efuse_parsing, > > + .probe = svs_mt8186_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > I know I gave you my R-b tag earlier, but I've just noticed that: > please remove > irqflags, as this kind of flags are specified in devicetree and it is > not > necessary to specify them here. > > Thanks, > Angelo Hi Angelo, Sure, I will remove it in the next version. Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 8:40 ` Tim Chang -1 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8195 svs compatible in dt-bindings. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index c86a5430641f..4bf26a333373 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8183-svs - mediatek,mt8186-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs reg: maxItems: 1 -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8195 svs compatible in dt-bindings. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index c86a5430641f..4bf26a333373 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8183-svs - mediatek,mt8186-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs reg: maxItems: 1 -- 2.18.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> Add mt8195 svs compatible in dt-bindings. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index c86a5430641f..4bf26a333373 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8183-svs - mediatek,mt8186-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs reg: maxItems: 1 -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 8:40 ` Tim Chang -1 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> To support svs on MT8195, add corresponding bank information, platform data, probe and parsing function. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> --- drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 656d0361ff7d..bb5021648143 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return 0; } +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm = svsp->efuse[0] & GENMASK(7, 0); + vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + if (vmin == 0x1) + svsb->vmin = 0x1e; + + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type == SVSB_LOW) { + svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type == SVSB_HIGH) { + svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + for (i = 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] != 0) + break; + + if (i == svsp->tefuse_max) + golden_temp = 50; /* All thermal efuse data are 0 */ + else + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 500; + svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2257,6 +2340,61 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) return 0; } +static struct svs_bank svs_mt8195_banks[] = { + { + .sw_id = SVSB_GPU, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 640000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_GPU, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu1", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 880000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] = { { .sw_id = SVSB_GPU, @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { }, }; +static const struct svs_platform_data svs_mt8195_platform_data = { + .name = "mt8195-svs", + .banks = svs_mt8195_banks, + .efuse_parsing = svs_mt8195_efuse_parsing, + .probe = svs_mt8192_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data = { .name = "mt8192-svs", .banks = svs_mt8192_banks, @@ -2591,6 +2739,9 @@ static const struct svs_platform_data svs_mt8183_platform_data = { static const struct of_device_id svs_of_match[] = { { + .compatible = "mediatek,mt8195-svs", + .data = &svs_mt8195_platform_data, + }, { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, }, { -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> To support svs on MT8195, add corresponding bank information, platform data, probe and parsing function. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> --- drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 656d0361ff7d..bb5021648143 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return 0; } +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm = svsp->efuse[0] & GENMASK(7, 0); + vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + if (vmin == 0x1) + svsb->vmin = 0x1e; + + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type == SVSB_LOW) { + svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type == SVSB_HIGH) { + svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + for (i = 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] != 0) + break; + + if (i == svsp->tefuse_max) + golden_temp = 50; /* All thermal efuse data are 0 */ + else + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 500; + svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2257,6 +2340,61 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) return 0; } +static struct svs_bank svs_mt8195_banks[] = { + { + .sw_id = SVSB_GPU, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 640000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_GPU, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu1", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 880000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] = { { .sw_id = SVSB_GPU, @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { }, }; +static const struct svs_platform_data svs_mt8195_platform_data = { + .name = "mt8195-svs", + .banks = svs_mt8195_banks, + .efuse_parsing = svs_mt8195_efuse_parsing, + .probe = svs_mt8192_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data = { .name = "mt8192-svs", .banks = svs_mt8192_banks, @@ -2591,6 +2739,9 @@ static const struct svs_platform_data svs_mt8183_platform_data = { static const struct of_device_id svs_of_match[] = { { + .compatible = "mediatek,mt8195-svs", + .data = &svs_mt8195_platform_data, + }, { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, }, { -- 2.18.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-23 8:40 ` Tim Chang 0 siblings, 0 replies; 33+ messages in thread From: Tim Chang @ 2022-05-23 8:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman, Jia-Wei Chang Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno From: Jia-Wei Chang <jia-wei.chang@mediatek.com> To support svs on MT8195, add corresponding bank information, platform data, probe and parsing function. Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> --- drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 656d0361ff7d..bb5021648143 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return 0; } +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i = 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm = svsp->efuse[0] & GENMASK(7, 0); + vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + if (vmin == 0x1) + svsb->vmin = 0x1e; + + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type == SVSB_LOW) { + svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type == SVSB_HIGH) { + svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax += svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /= sizeof(u32); + nvmem_cell_put(cell); + + for (i = 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] != 0) + break; + + if (i == svsp->tefuse_max) + golden_temp = 50; /* All thermal efuse data are 0 */ + else + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svsb->mts = 500; + svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2257,6 +2340,61 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) return 0; } +static struct svs_bank svs_mt8195_banks[] = { + { + .sw_id = SVSB_GPU, + .type = SVSB_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 640000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + }, + { + .sw_id = SVSB_GPU, + .type = SVSB_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu1", + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = MAX_OPP_ENTRIES, + .freq_base = 880000000, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .vmax = 0x38, + .vmin = 0x14, + .age_config = 0x555555, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x18, + .chk_shift = 0x87, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] = { { .sw_id = SVSB_GPU, @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { }, }; +static const struct svs_platform_data svs_mt8195_platform_data = { + .name = "mt8195-svs", + .banks = svs_mt8195_banks, + .efuse_parsing = svs_mt8195_efuse_parsing, + .probe = svs_mt8192_platform_probe, + .irqflags = IRQF_TRIGGER_HIGH, + .regs = svs_regs_v2, + .bank_max = ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data = { .name = "mt8192-svs", .banks = svs_mt8192_banks, @@ -2591,6 +2739,9 @@ static const struct svs_platform_data svs_mt8183_platform_data = { static const struct of_device_id svs_of_match[] = { { + .compatible = "mediatek,mt8195-svs", + .data = &svs_mt8195_platform_data, + }, { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data, }, { -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno -1 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > To support svs on MT8195, add corresponding bank information, platform > data, probe and parsing function. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > --- > drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ > 1 file changed, 151 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 656d0361ff7d..bb5021648143 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) ..snip.. > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { > }, > }; > > +static const struct svs_platform_data svs_mt8195_platform_data = { > + .name = "mt8195-svs", > + .banks = svs_mt8195_banks, > + .efuse_parsing = svs_mt8195_efuse_parsing, > + .probe = svs_mt8192_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, Interrupt flags are specified in devicetree; avoid declaring irqflags. After that: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > To support svs on MT8195, add corresponding bank information, platform > data, probe and parsing function. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > --- > drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ > 1 file changed, 151 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 656d0361ff7d..bb5021648143 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) ..snip.. > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { > }, > }; > > +static const struct svs_platform_data svs_mt8195_platform_data = { > + .name = "mt8195-svs", > + .banks = svs_mt8195_banks, > + .efuse_parsing = svs_mt8195_efuse_parsing, > + .probe = svs_mt8192_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, Interrupt flags are specified in devicetree; avoid declaring irqflags. After that: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-23 9:38 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 33+ messages in thread From: AngeloGioacchino Del Regno @ 2022-05-23 9:38 UTC (permalink / raw) To: Tim Chang, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi Il 23/05/22 10:40, Tim Chang ha scritto: > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > To support svs on MT8195, add corresponding bank information, platform > data, probe and parsing function. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > --- > drivers/soc/mediatek/mtk-svs.c | 151 +++++++++++++++++++++++++++++++++ > 1 file changed, 151 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c > index 656d0361ff7d..bb5021648143 100644 > --- a/drivers/soc/mediatek/mtk-svs.c > +++ b/drivers/soc/mediatek/mtk-svs.c > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) ..snip.. > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = { > }, > }; > > +static const struct svs_platform_data svs_mt8195_platform_data = { > + .name = "mt8195-svs", > + .banks = svs_mt8195_banks, > + .efuse_parsing = svs_mt8195_efuse_parsing, > + .probe = svs_mt8192_platform_probe, > + .irqflags = IRQF_TRIGGER_HIGH, Interrupt flags are specified in devicetree; avoid declaring irqflags. After that: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 2022-05-23 9:38 ` AngeloGioacchino Del Regno (?) @ 2022-05-26 5:54 ` Jia-Wei Chang -1 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:54 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > To support svs on MT8195, add corresponding bank information, > > platform > > data, probe and parsing function. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > > --- > > drivers/soc/mediatek/mtk-svs.c | 151 > > +++++++++++++++++++++++++++++++++ > > 1 file changed, 151 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 656d0361ff7d..bb5021648143 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct > > svs_platform *svsp) > > ..snip.. > > > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = > > { > > }, > > }; > > > > +static const struct svs_platform_data svs_mt8195_platform_data = { > > + .name = "mt8195-svs", > > + .banks = svs_mt8195_banks, > > + .efuse_parsing = svs_mt8195_efuse_parsing, > > + .probe = svs_mt8192_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > Interrupt flags are specified in devicetree; avoid declaring > irqflags. > > After that: > > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Hi Angelo, Sure, I will remove it in the next version. Thanks. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-26 5:54 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:54 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > To support svs on MT8195, add corresponding bank information, > > platform > > data, probe and parsing function. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > > --- > > drivers/soc/mediatek/mtk-svs.c | 151 > > +++++++++++++++++++++++++++++++++ > > 1 file changed, 151 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 656d0361ff7d..bb5021648143 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct > > svs_platform *svsp) > > ..snip.. > > > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = > > { > > }, > > }; > > > > +static const struct svs_platform_data svs_mt8195_platform_data = { > > + .name = "mt8195-svs", > > + .banks = svs_mt8195_banks, > > + .efuse_parsing = svs_mt8195_efuse_parsing, > > + .probe = svs_mt8192_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > Interrupt flags are specified in devicetree; avoid declaring > irqflags. > > After that: > > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Hi Angelo, Sure, I will remove it in the next version. Thanks. ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 @ 2022-05-26 5:54 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-26 5:54 UTC (permalink / raw) To: AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi On Mon, 2022-05-23 at 11:38 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 10:40, Tim Chang ha scritto: > > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > To support svs on MT8195, add corresponding bank information, > > platform > > data, probe and parsing function. > > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > > > > --- > > drivers/soc/mediatek/mtk-svs.c | 151 > > +++++++++++++++++++++++++++++++++ > > 1 file changed, 151 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-svs.c > > b/drivers/soc/mediatek/mtk-svs.c > > index 656d0361ff7d..bb5021648143 100644 > > --- a/drivers/soc/mediatek/mtk-svs.c > > +++ b/drivers/soc/mediatek/mtk-svs.c > > @@ -1680,6 +1680,89 @@ static int svs_bank_resource_setup(struct > > svs_platform *svsp) > > ..snip.. > > > @@ -2559,6 +2697,16 @@ static struct svs_bank svs_mt8183_banks[] = > > { > > }, > > }; > > > > +static const struct svs_platform_data svs_mt8195_platform_data = { > > + .name = "mt8195-svs", > > + .banks = svs_mt8195_banks, > > + .efuse_parsing = svs_mt8195_efuse_parsing, > > + .probe = svs_mt8192_platform_probe, > > + .irqflags = IRQF_TRIGGER_HIGH, > > Interrupt flags are specified in devicetree; avoid declaring > irqflags. > > After that: > > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Hi Angelo, Sure, I will remove it in the next version. Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and 2022-05-23 8:40 ` Tim Chang (?) @ 2022-05-23 8:57 ` Jia-Wei Chang -1 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-23 8:57 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno On Mon, 2022-05-23 at 16:40 +0800, Tim Chang wrote: The Subject is for [Patch v3 0/4] rather than v2. Sorry for my typo. > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) > hardware which used as optimization of opp voltage table for > corresponding dvfs drivers. > > This series is based on Roger's series [1]. > [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com > > Change since v2: > - Reuse platform probe of MT8192 for MT8195. > - Remove unnecessary svs bank parameters of MT8195. > - Remove sw id check for MT8195 efuse parsing. > > Change since v1: > - Add myself as a co-maintainer of mtk-svs.yaml. > - Fix MT8186 error handling in platform probe. > - Add dt-bindings and support for MT8195 platform. > > Jia-Wei Chang (4): > dt-bindings: soc: mediatek: add mt8186 svs dt-bindings > soc: mediatek: svs: add support for mt8186 > dt-bindings: soc: mediatek: add mt8195 svs dt-bindings > soc: mediatek: svs: add support for mt8195 > > .../bindings/soc/mediatek/mtk-svs.yaml | 3 + > drivers/soc/mediatek/mtk-svs.c | 502 > +++++++++++++++++- > 2 files changed, 498 insertions(+), 7 deletions(-) > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and @ 2022-05-23 8:57 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-23 8:57 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno On Mon, 2022-05-23 at 16:40 +0800, Tim Chang wrote: The Subject is for [Patch v3 0/4] rather than v2. Sorry for my typo. > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) > hardware which used as optimization of opp voltage table for > corresponding dvfs drivers. > > This series is based on Roger's series [1]. > [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com > > Change since v2: > - Reuse platform probe of MT8192 for MT8195. > - Remove unnecessary svs bank parameters of MT8195. > - Remove sw id check for MT8195 efuse parsing. > > Change since v1: > - Add myself as a co-maintainer of mtk-svs.yaml. > - Fix MT8186 error handling in platform probe. > - Add dt-bindings and support for MT8195 platform. > > Jia-Wei Chang (4): > dt-bindings: soc: mediatek: add mt8186 svs dt-bindings > soc: mediatek: svs: add support for mt8186 > dt-bindings: soc: mediatek: add mt8195 svs dt-bindings > soc: mediatek: svs: add support for mt8195 > > .../bindings/soc/mediatek/mtk-svs.yaml | 3 + > drivers/soc/mediatek/mtk-svs.c | 502 > +++++++++++++++++- > 2 files changed, 498 insertions(+), 7 deletions(-) > ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and @ 2022-05-23 8:57 ` Jia-Wei Chang 0 siblings, 0 replies; 33+ messages in thread From: Jia-Wei Chang @ 2022-05-23 8:57 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel, Roger Lu, Kevin Hilman Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, Project_Global_Chrome_Upstream_Group, hsinyi, AngeloGioacchino Del Regno On Mon, 2022-05-23 at 16:40 +0800, Tim Chang wrote: The Subject is for [Patch v3 0/4] rather than v2. Sorry for my typo. > From: Jia-Wei Chang <jia-wei.chang@mediatek.com> > > This series supports MT8186 and MT8195 Smart Voltage Scaling (SVS) > hardware which used as optimization of opp voltage table for > corresponding dvfs drivers. > > This series is based on Roger's series [1]. > [1]: Message ID: 20220516004311.18358-1-roger.lu@mediatek.com > > Change since v2: > - Reuse platform probe of MT8192 for MT8195. > - Remove unnecessary svs bank parameters of MT8195. > - Remove sw id check for MT8195 efuse parsing. > > Change since v1: > - Add myself as a co-maintainer of mtk-svs.yaml. > - Fix MT8186 error handling in platform probe. > - Add dt-bindings and support for MT8195 platform. > > Jia-Wei Chang (4): > dt-bindings: soc: mediatek: add mt8186 svs dt-bindings > soc: mediatek: svs: add support for mt8186 > dt-bindings: soc: mediatek: add mt8195 svs dt-bindings > soc: mediatek: svs: add support for mt8195 > > .../bindings/soc/mediatek/mtk-svs.yaml | 3 + > drivers/soc/mediatek/mtk-svs.c | 502 > +++++++++++++++++- > 2 files changed, 498 insertions(+), 7 deletions(-) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2022-05-26 6:03 UTC | newest] Thread overview: 33+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-05-23 8:40 [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` [PATCH v3 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-24 2:05 ` Rob Herring 2022-05-24 2:05 ` Rob Herring 2022-05-24 2:05 ` Rob Herring 2022-05-23 8:40 ` [PATCH v3 2/4] soc: mediatek: svs: add support for mt8186 Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-26 5:52 ` Jia-Wei Chang 2022-05-26 5:52 ` Jia-Wei Chang 2022-05-26 5:52 ` Jia-Wei Chang 2022-05-23 8:40 ` [PATCH v3 3/4] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` [PATCH v3 4/4] soc: mediatek: svs: add support for mt8195 Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 8:40 ` Tim Chang 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-23 9:38 ` AngeloGioacchino Del Regno 2022-05-26 5:54 ` Jia-Wei Chang 2022-05-26 5:54 ` Jia-Wei Chang 2022-05-26 5:54 ` Jia-Wei Chang 2022-05-23 8:57 ` [PATCH v2 0/4] soc: mediatek: svs: add support for mt8186 and Jia-Wei Chang 2022-05-23 8:57 ` Jia-Wei Chang 2022-05-23 8:57 ` Jia-Wei Chang
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.