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From: Jakub Kicinski <kuba@kernel.org>
To: Vadim Fedorenko <vfedorenko@novek.ru>
Cc: "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
	Vadim Fedorenko <vadfed@fb.com>, Aya Levin <ayal@nvidia.com>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Jonathan Lemon <jonathan.lemon@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	Richard Cochran <richardcochran@gmail.com>
Subject: Re: [RFC PATCH v1 1/3] dpll: Add DPLL framework base functions
Date: Thu, 30 Jun 2022 11:27:42 -0700	[thread overview]
Message-ID: <20220630112742.0a1d0bf0@kernel.org> (raw)
In-Reply-To: <689711e9-47ca-af2d-b0a7-a6406d9736e1@novek.ru>

On Thu, 30 Jun 2022 16:50:46 +0100 Vadim Fedorenko wrote:
> On 30.06.2022 03:23, Jakub Kicinski wrote:
>> On Thu, 30 Jun 2022 00:30:08 +0100 Vadim Fedorenko wrote:  
>>> This way it's getting closer and closer to ptp, but still having phase offset is
>>> fair point and I will go this way. Jakub, do you have any objections?  
>> 
>> How does the DPLL interface interact with PTP? Either API can set the
>> phase.  
> 
> Well, if the same hardware is exposed to both subsystem, it will be serialised 
> by hardware driver. And it goes to hardware implementation on how to deal with 
> such changes. Am I wrong?

That's what ends up happening in practice. But it's a pretty poor
experience for everyone involved :(

Stating the obvious, perhaps, but the goal should be that either the
APIs are disjoint or one is a superset of the other and there can be 
a kernel translation layer so that the driver only has to implement 
one.

By a quick look at the PTP header it has phase offsets for both the
clock and the outputs? Not sure. Don't see much in the docs either.

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WARNING: multiple messages have this Message-ID (diff)
From: Jakub Kicinski <kuba@kernel.org>
To: Vadim Fedorenko <vfedorenko@novek.ru>
Cc: "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
	Vadim Fedorenko <vadfed@fb.com>, Aya Levin <ayal@nvidia.com>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Jonathan Lemon <jonathan.lemon@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	Richard Cochran <richardcochran@gmail.com>
Subject: Re: [RFC PATCH v1 1/3] dpll: Add DPLL framework base functions
Date: Thu, 30 Jun 2022 11:27:42 -0700	[thread overview]
Message-ID: <20220630112742.0a1d0bf0@kernel.org> (raw)
In-Reply-To: <689711e9-47ca-af2d-b0a7-a6406d9736e1@novek.ru>

On Thu, 30 Jun 2022 16:50:46 +0100 Vadim Fedorenko wrote:
> On 30.06.2022 03:23, Jakub Kicinski wrote:
>> On Thu, 30 Jun 2022 00:30:08 +0100 Vadim Fedorenko wrote:  
>>> This way it's getting closer and closer to ptp, but still having phase offset is
>>> fair point and I will go this way. Jakub, do you have any objections?  
>> 
>> How does the DPLL interface interact with PTP? Either API can set the
>> phase.  
> 
> Well, if the same hardware is exposed to both subsystem, it will be serialised 
> by hardware driver. And it goes to hardware implementation on how to deal with 
> such changes. Am I wrong?

That's what ends up happening in practice. But it's a pretty poor
experience for everyone involved :(

Stating the obvious, perhaps, but the goal should be that either the
APIs are disjoint or one is a superset of the other and there can be 
a kernel translation layer so that the driver only has to implement 
one.

By a quick look at the PTP header it has phase offsets for both the
clock and the outputs? Not sure. Don't see much in the docs either.

  reply	other threads:[~2022-06-30 18:28 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-23  0:57 [RFC PATCH v1 0/3] Create common DPLL/clock configuration API Vadim Fedorenko
2022-06-23  0:57 ` Vadim Fedorenko
2022-06-23  0:57 ` [RFC PATCH v1 1/3] dpll: Add DPLL framework base functions Vadim Fedorenko
2022-06-23  0:57   ` Vadim Fedorenko
2022-06-23 15:33   ` Kubalewski, Arkadiusz
2022-06-23 15:33     ` Kubalewski, Arkadiusz
2022-06-23 22:48     ` Vadim Fedorenko
2022-06-23 22:48       ` Vadim Fedorenko
2022-06-24 17:36       ` Kubalewski, Arkadiusz
2022-06-24 17:36         ` Kubalewski, Arkadiusz
2022-06-26 19:39         ` Vadim Fedorenko
2022-06-26 19:39           ` Vadim Fedorenko
2022-06-29  1:46           ` Kubalewski, Arkadiusz
2022-06-29  1:46             ` Kubalewski, Arkadiusz
2022-06-29 23:30             ` Vadim Fedorenko
2022-06-29 23:30               ` Vadim Fedorenko
2022-06-30 10:00               ` Kubalewski, Arkadiusz
2022-06-30 10:00                 ` Kubalewski, Arkadiusz
     [not found]               ` <20220629192312.45acd2fd@kernel.org>
2022-06-30 15:50                 ` Vadim Fedorenko
2022-06-30 15:50                   ` Vadim Fedorenko
2022-06-30 18:27                   ` Jakub Kicinski [this message]
2022-06-30 18:27                     ` Jakub Kicinski
2022-06-23  0:57 ` [RFC PATCH v1 2/3] dpll: add netlink events Vadim Fedorenko
2022-06-23  0:57   ` Vadim Fedorenko
2022-06-23  0:57 ` [RFC PATCH v1 3/3] ptp_ocp: implement DPLL ops Vadim Fedorenko
2022-06-23  0:57   ` Vadim Fedorenko
2022-06-23 18:28   ` Jonathan Lemon
2022-06-23 18:28     ` Jonathan Lemon
2022-06-23 23:11     ` Vadim Fedorenko
2022-06-23 23:11       ` Vadim Fedorenko
2022-06-23 23:36       ` Jonathan Lemon
2022-06-23 23:36         ` Jonathan Lemon
2022-06-26 19:28         ` Vadim Fedorenko
2022-06-26 19:28           ` Vadim Fedorenko
2022-06-27 19:27           ` Jonathan Lemon
2022-06-27 19:27             ` Jonathan Lemon
2022-06-27 22:06             ` Vadim Fedorenko
2022-06-27 22:06               ` Vadim Fedorenko
2022-06-26 19:27     ` Vadim Fedorenko
2022-06-26 19:27       ` Vadim Fedorenko
2022-06-27 19:23       ` Jonathan Lemon
2022-06-27 19:23         ` Jonathan Lemon
2022-06-27 22:04         ` Vadim Fedorenko
2022-06-27 22:04           ` Vadim Fedorenko
2022-06-24 17:20 ` [RFC PATCH v1 0/3] Create common DPLL/clock configuration API Florian Fainelli
2022-06-24 17:20   ` Florian Fainelli
2022-06-24 17:55   ` Jakub Kicinski
2022-06-24 17:55     ` Jakub Kicinski

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