From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Parikshit Pareek <quic_ppareek@quicinc.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Johan Hovold <johan@kernel.org>, Andy Gross <agross@kernel.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>,
Prasanna Kumar <quic_kprasan@quicinc.com>,
linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v2] arm64: dts: qcom: sc8280xp: fix apps_smmu irq
Date: Fri, 15 Jul 2022 13:50:36 +0530 [thread overview]
Message-ID: <20220715082036.GA12197@workstation> (raw)
In-Reply-To: <7290abc3-8ec7-8128-9d29-651e9b8aa861@quicinc.com>
On Thu, Jul 14, 2022 at 12:37:45PM +0530, Sai Prakash Ranjan wrote:
> Hi Mani,
>
> On 7/12/2022 11:56 PM, Manivannan Sadhasivam wrote:
> > On Tue, Jul 12, 2022 at 07:41:14PM +0300, Dmitry Baryshkov wrote:
> > > On Tue, 12 Jul 2022 at 19:24, Johan Hovold <johan@kernel.org> wrote:
> > > > On Tue, Jul 12, 2022 at 08:10:44PM +0530, Manivannan Sadhasivam wrote:
> > > > > On Tue, Jul 12, 2022 at 07:30:09PM +0530, Parikshit Pareek wrote:
> > > > > > Wrong values have been introduced for interrupts property. Fix those
> > > > > > ones, and correct the mapping of context banks to irq number.
> > > > > >
> > > > > And you ignored my comment about sorting the IRQs...
> > > > Isn't the order significant here? Either way, that would be a separate
> > > > change that shouldn't be merged with the fix.
> > > I'd tend to agree here. Let's get the fix in first and sort the IRQs
> > > in a separate commit. The order of them is strange indeed.
> > >
>
> As per "arm,smmu.yaml" devicetree documentation, context interrupts are specified in order of their indexing by the SMMU
> and not the IRQ numbers, quoting relevant part below.
>
> "Interrupt list, with the first #global-interrupts entries corresponding to the global interrupts
> and any following entries corresponding to context interrupts, specified in order of their indexing by the SMMU."
>
> And the current order in DT without sorting by IRQ number matches with the SMMU IP interrupt document,
>
> For example, in the current DT order, you see 409 and then 418 instead of 410. Here 409 is app_tcu_cxt_irpt_vec[73],
> 418 is app_tcu_cxt_irpt_vec[74] and 410 is app_tcu_cxt_irpt_vec[90] and hence the ordering of 409, 418 .... 410.
> Also the reverse ordering at the end from 913 to 891 is also as per this indexing.
>
> So the current ordering is proper and do not require sorting.
>
Ah, I missed reading the binding. Sorry for the noise.
> As for the missing IRQs and duplicate ones, I will reply on the patch, looks like there are some other misconfigurations as well.
>
Thanks,
Mani
> Thanks,
> Sai
>
next prev parent reply other threads:[~2022-07-15 8:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-12 14:00 [PATCH v2] arm64: dts: qcom: sc8280xp: fix apps_smmu irq Parikshit Pareek
2022-07-12 14:40 ` Manivannan Sadhasivam
2022-07-12 16:11 ` Parikshit Pareek
2022-07-12 16:24 ` Johan Hovold
2022-07-12 16:41 ` Dmitry Baryshkov
2022-07-12 18:26 ` Manivannan Sadhasivam
2022-07-14 7:07 ` Sai Prakash Ranjan
2022-07-15 8:20 ` Manivannan Sadhasivam [this message]
2022-07-12 16:22 ` Johan Hovold
2022-07-12 16:41 ` Andrew Halaney
2022-07-14 7:17 ` Sai Prakash Ranjan
2022-07-15 8:08 ` Sai Prakash Ranjan
2022-07-15 8:13 ` Sai Prakash Ranjan
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