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From: Rob Herring <robh@kernel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
	chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com,
	mbrugger@suse.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, kernel@collabora.com,
	nfraprado@collabora.com
Subject: Re: [PATCH 2/3] dt-bindings: power: mediatek: Update example to use phandle to syscon
Date: Mon, 18 Jul 2022 12:06:54 -0600	[thread overview]
Message-ID: <20220718180654.GA3260460-robh@kernel.org> (raw)
In-Reply-To: <20220711122503.286743-3-angelogioacchino.delregno@collabora.com>

On Mon, Jul 11, 2022 at 02:25:02PM +0200, AngeloGioacchino Del Regno wrote:
> The preferred way of declaring this node is by using a phandle to
> syscon: update the example to reflect that.

Preferred by who? Not me. 
 
What problem are you trying to solve? Better be a good reason for 
breaking compatibility.


> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../power/mediatek,power-controller.yaml      | 125 +++++++++---------
>  1 file changed, 63 insertions(+), 62 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index 848fdff7c9d8..bed059e4401d 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -237,76 +237,77 @@ examples:
>          scpsys: syscon@10006000 {
>              compatible = "syscon", "simple-mfd";

Only generic compatibles is certainly not preferred.

>              reg = <0 0x10006000 0 0x1000>;
> +        };
> +    };
>  
> -            spm: power-controller {
> -                compatible = "mediatek,mt8173-power-controller";
> +    spm: power-controller {
> +        compatible = "mediatek,mt8173-power-controller";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        #power-domain-cells = <1>;
> +        syscon = <&scpsys>;
> +
> +        /* power domains of the SoC */
> +        power-domain@MT8173_POWER_DOMAIN_VDEC {
> +            reg = <MT8173_POWER_DOMAIN_VDEC>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_VENC {
> +            reg = <MT8173_POWER_DOMAIN_VENC>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>,
> +                     <&topckgen CLK_TOP_VENC_SEL>;
> +            clock-names = "mm", "venc";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_ISP {
> +            reg = <MT8173_POWER_DOMAIN_ISP>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_MM {
> +            reg = <MT8173_POWER_DOMAIN_MM>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +            mediatek,infracfg = <&infracfg>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> +            reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>,
> +                     <&topckgen CLK_TOP_VENC_LT_SEL>;
> +            clock-names = "mm", "venclt";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_AUDIO {
> +            reg = <MT8173_POWER_DOMAIN_AUDIO>;
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_USB {
> +            reg = <MT8173_POWER_DOMAIN_USB>;
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> +            reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> +            clocks = <&clk26m>;
> +            clock-names = "mfg";
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            #power-domain-cells = <1>;
> +
> +            power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> +                reg = <MT8173_POWER_DOMAIN_MFG_2D>;
>                  #address-cells = <1>;
>                  #size-cells = <0>;
>                  #power-domain-cells = <1>;
>  
> -                /* power domains of the SoC */
> -                power-domain@MT8173_POWER_DOMAIN_VDEC {
> -                    reg = <MT8173_POWER_DOMAIN_VDEC>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_VENC {
> -                    reg = <MT8173_POWER_DOMAIN_VENC>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>,
> -                             <&topckgen CLK_TOP_VENC_SEL>;
> -                    clock-names = "mm", "venc";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_ISP {
> -                    reg = <MT8173_POWER_DOMAIN_ISP>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_MM {
> -                    reg = <MT8173_POWER_DOMAIN_MM>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> +                power-domain@MT8173_POWER_DOMAIN_MFG {
> +                    reg = <MT8173_POWER_DOMAIN_MFG>;
>                      #power-domain-cells = <0>;
>                      mediatek,infracfg = <&infracfg>;
>                  };
> -                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> -                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>,
> -                             <&topckgen CLK_TOP_VENC_LT_SEL>;
> -                    clock-names = "mm", "venclt";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_AUDIO {
> -                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_USB {
> -                    reg = <MT8173_POWER_DOMAIN_USB>;
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> -                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> -                    clocks = <&clk26m>;
> -                    clock-names = "mfg";
> -                    #address-cells = <1>;
> -                    #size-cells = <0>;
> -                    #power-domain-cells = <1>;
> -
> -                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> -                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
> -                        #address-cells = <1>;
> -                        #size-cells = <0>;
> -                        #power-domain-cells = <1>;
> -
> -                        power-domain@MT8173_POWER_DOMAIN_MFG {
> -                            reg = <MT8173_POWER_DOMAIN_MFG>;
> -                            #power-domain-cells = <0>;
> -                            mediatek,infracfg = <&infracfg>;
> -                        };
> -                    };
> -                };
>              };
>          };
>      };
> -- 
> 2.35.1
> 
> 


WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
	chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com,
	mbrugger@suse.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, kernel@collabora.com,
	nfraprado@collabora.com
Subject: Re: [PATCH 2/3] dt-bindings: power: mediatek: Update example to use phandle to syscon
Date: Mon, 18 Jul 2022 12:06:54 -0600	[thread overview]
Message-ID: <20220718180654.GA3260460-robh@kernel.org> (raw)
In-Reply-To: <20220711122503.286743-3-angelogioacchino.delregno@collabora.com>

On Mon, Jul 11, 2022 at 02:25:02PM +0200, AngeloGioacchino Del Regno wrote:
> The preferred way of declaring this node is by using a phandle to
> syscon: update the example to reflect that.

Preferred by who? Not me. 
 
What problem are you trying to solve? Better be a good reason for 
breaking compatibility.


> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../power/mediatek,power-controller.yaml      | 125 +++++++++---------
>  1 file changed, 63 insertions(+), 62 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index 848fdff7c9d8..bed059e4401d 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -237,76 +237,77 @@ examples:
>          scpsys: syscon@10006000 {
>              compatible = "syscon", "simple-mfd";

Only generic compatibles is certainly not preferred.

>              reg = <0 0x10006000 0 0x1000>;
> +        };
> +    };
>  
> -            spm: power-controller {
> -                compatible = "mediatek,mt8173-power-controller";
> +    spm: power-controller {
> +        compatible = "mediatek,mt8173-power-controller";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        #power-domain-cells = <1>;
> +        syscon = <&scpsys>;
> +
> +        /* power domains of the SoC */
> +        power-domain@MT8173_POWER_DOMAIN_VDEC {
> +            reg = <MT8173_POWER_DOMAIN_VDEC>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_VENC {
> +            reg = <MT8173_POWER_DOMAIN_VENC>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>,
> +                     <&topckgen CLK_TOP_VENC_SEL>;
> +            clock-names = "mm", "venc";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_ISP {
> +            reg = <MT8173_POWER_DOMAIN_ISP>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_MM {
> +            reg = <MT8173_POWER_DOMAIN_MM>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>;
> +            clock-names = "mm";
> +            #power-domain-cells = <0>;
> +            mediatek,infracfg = <&infracfg>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> +            reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> +            clocks = <&topckgen CLK_TOP_MM_SEL>,
> +                     <&topckgen CLK_TOP_VENC_LT_SEL>;
> +            clock-names = "mm", "venclt";
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_AUDIO {
> +            reg = <MT8173_POWER_DOMAIN_AUDIO>;
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_USB {
> +            reg = <MT8173_POWER_DOMAIN_USB>;
> +            #power-domain-cells = <0>;
> +        };
> +        power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> +            reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> +            clocks = <&clk26m>;
> +            clock-names = "mfg";
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            #power-domain-cells = <1>;
> +
> +            power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> +                reg = <MT8173_POWER_DOMAIN_MFG_2D>;
>                  #address-cells = <1>;
>                  #size-cells = <0>;
>                  #power-domain-cells = <1>;
>  
> -                /* power domains of the SoC */
> -                power-domain@MT8173_POWER_DOMAIN_VDEC {
> -                    reg = <MT8173_POWER_DOMAIN_VDEC>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_VENC {
> -                    reg = <MT8173_POWER_DOMAIN_VENC>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>,
> -                             <&topckgen CLK_TOP_VENC_SEL>;
> -                    clock-names = "mm", "venc";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_ISP {
> -                    reg = <MT8173_POWER_DOMAIN_ISP>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_MM {
> -                    reg = <MT8173_POWER_DOMAIN_MM>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>;
> -                    clock-names = "mm";
> +                power-domain@MT8173_POWER_DOMAIN_MFG {
> +                    reg = <MT8173_POWER_DOMAIN_MFG>;
>                      #power-domain-cells = <0>;
>                      mediatek,infracfg = <&infracfg>;
>                  };
> -                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> -                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> -                    clocks = <&topckgen CLK_TOP_MM_SEL>,
> -                             <&topckgen CLK_TOP_VENC_LT_SEL>;
> -                    clock-names = "mm", "venclt";
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_AUDIO {
> -                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_USB {
> -                    reg = <MT8173_POWER_DOMAIN_USB>;
> -                    #power-domain-cells = <0>;
> -                };
> -                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> -                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> -                    clocks = <&clk26m>;
> -                    clock-names = "mfg";
> -                    #address-cells = <1>;
> -                    #size-cells = <0>;
> -                    #power-domain-cells = <1>;
> -
> -                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> -                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
> -                        #address-cells = <1>;
> -                        #size-cells = <0>;
> -                        #power-domain-cells = <1>;
> -
> -                        power-domain@MT8173_POWER_DOMAIN_MFG {
> -                            reg = <MT8173_POWER_DOMAIN_MFG>;
> -                            #power-domain-cells = <0>;
> -                            mediatek,infracfg = <&infracfg>;
> -                        };
> -                    };
> -                };
>              };
>          };
>      };
> -- 
> 2.35.1
> 
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-07-18 18:07 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-11 12:25 [PATCH 0/3] mtk-pm-domains: Use 'syscon' phandle for SCPSYS regmap AngeloGioacchino Del Regno
2022-07-11 12:25 ` AngeloGioacchino Del Regno
2022-07-11 12:25 ` [PATCH 1/3] dt-bindings: power: mediatek: Document phandle to SCPSYS syscon node AngeloGioacchino Del Regno
2022-07-11 12:25   ` AngeloGioacchino Del Regno
2022-07-12  8:31   ` Krzysztof Kozlowski
2022-07-12  8:31     ` Krzysztof Kozlowski
2022-07-11 12:25 ` [PATCH 2/3] dt-bindings: power: mediatek: Update example to use phandle to syscon AngeloGioacchino Del Regno
2022-07-11 12:25   ` AngeloGioacchino Del Regno
2022-07-18 18:06   ` Rob Herring [this message]
2022-07-18 18:06     ` Rob Herring
2022-07-19  7:57     ` AngeloGioacchino Del Regno
2022-07-19  7:57       ` AngeloGioacchino Del Regno
2022-07-11 12:25 ` [PATCH 3/3] soc: mediatek: pm-domains: Grab SCPSYS registers from " AngeloGioacchino Del Regno
2022-07-11 12:25   ` AngeloGioacchino Del Regno
2022-07-12  8:39   ` Krzysztof Kozlowski
2022-07-12  8:39     ` Krzysztof Kozlowski

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