From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <qemu-devel@nongnu.org>, "Michael S . Tsirkin" <mst@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
Igor Mammedov <imammedo@redhat.com>
Cc: <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH 2/2] hw/cxl: Fix wrong query of target ports
Date: Mon, 8 Aug 2022 13:20:51 +0100 [thread overview]
Message-ID: <20220808122051.14822-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220808122051.14822-1-Jonathan.Cameron@huawei.com>
Two issues were present in this code:
1) Check on which register to look in was inverted.
2) Both branches use the _LO register.
Whilst here moved to extract32() rather than hand rolling
the field extraction as simpler and hopefully less error prone.
Fixes Coverity CID: 1488873
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-host.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index faa68ef038..1adf61231a 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -104,7 +104,6 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
uint32_t ctrl;
uint32_t ig_enc;
uint32_t iw_enc;
- uint32_t target_reg;
uint32_t target_idx;
ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
@@ -116,14 +115,13 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
- if (target_idx > 4) {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= target_idx * 8;
+ if (target_idx < 4) {
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
+ target_idx * 8, 8);
} else {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= (target_idx - 4) * 8;
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
+ (target_idx - 4) * 8, 8);
}
- *target = target_reg & 0xff;
return true;
}
--
2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, "Michael S . Tsirkin" <mst@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
Igor Mammedov <imammedo@redhat.com>
Cc: <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH 2/2] hw/cxl: Fix wrong query of target ports
Date: Mon, 8 Aug 2022 13:20:51 +0100 [thread overview]
Message-ID: <20220808122051.14822-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220808122051.14822-1-Jonathan.Cameron@huawei.com>
Two issues were present in this code:
1) Check on which register to look in was inverted.
2) Both branches use the _LO register.
Whilst here moved to extract32() rather than hand rolling
the field extraction as simpler and hopefully less error prone.
Fixes Coverity CID: 1488873
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-host.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index faa68ef038..1adf61231a 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -104,7 +104,6 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
uint32_t ctrl;
uint32_t ig_enc;
uint32_t iw_enc;
- uint32_t target_reg;
uint32_t target_idx;
ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
@@ -116,14 +115,13 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
- if (target_idx > 4) {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= target_idx * 8;
+ if (target_idx < 4) {
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
+ target_idx * 8, 8);
} else {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= (target_idx - 4) * 8;
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
+ (target_idx - 4) * 8, 8);
}
- *target = target_reg & 0xff;
return true;
}
--
2.32.0
next prev parent reply other threads:[~2022-08-08 12:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-08 12:20 [PATCH 0/2] hw/cxl: Two CXL emulation fixes Jonathan Cameron
2022-08-08 12:20 ` Jonathan Cameron via
2022-08-08 12:20 ` [PATCH 1/2] hw/cxl: Fix memory leak in error paths Jonathan Cameron
2022-08-08 12:20 ` Jonathan Cameron via
2022-08-08 12:20 ` Jonathan Cameron [this message]
2022-08-08 12:20 ` [PATCH 2/2] hw/cxl: Fix wrong query of target ports Jonathan Cameron via
2022-08-17 11:45 ` [PATCH 0/2] hw/cxl: Two CXL emulation fixes Jonathan Cameron
2022-08-17 11:45 ` Jonathan Cameron via
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