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* [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings
@ 2022-08-16 21:06 ` Matt Roper
  0 siblings, 0 replies; 9+ messages in thread
From: Matt Roper @ 2022-08-16 21:06 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi, dri-devel

The bspec performance tuning section gives recommended settings that the
driver should program for various MMIO registers.  Although these
settings aren't "workarounds" we use the workaround infrastructure to do
this programming to make sure it is handled at the appropriate places
and doesn't conflict with any real workarounds.

Since more of these are starting to show up on recent platforms, it's a
good time to create a dedicated function to hold them so that there's
less ambiguity about how/where to implement new ones.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 42 ++++++++++++++-------
 1 file changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 59cf28baa472..a68d279b01f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2102,13 +2102,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		/* Wa_1509235366:dg2 */
 		wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
 			    GLOBAL_INVALIDATION_MODE);
-
-		/*
-		 * The following are not actually "workarounds" but rather
-		 * recommended tuning settings documented in the bspec's
-		 * performance guide section.
-		 */
-		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
 	}
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
@@ -2676,6 +2669,32 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 }
 
+/*
+ * The bspec performance guide has recommended MMIO tuning settings.  These
+ * aren't truly "workarounds" but we want to program them with the same
+ * workaround infrastructure to ensure that they're automatically added to
+ * the GuC save/restore lists, re-applied at the right times, and checked for
+ * any conflicting programming requested by real workarounds.
+ *
+ * Programming settings should be added here only if their registers are not
+ * part of an engine's register state context.  If a register is part of a
+ * context, then any tuning settings should be programmed in an appropriate
+ * function invoked by __intel_engine_init_ctx_wa().
+ */
+static void
+add_render_compute_tuning_settings(struct drm_i915_private *i915,
+				   struct i915_wa_list *wal)
+{
+	if (IS_PONTEVECCHIO(i915)) {
+		wa_write(wal, XEHPC_L3SCRUB,
+			 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+	}
+
+	if (IS_DG2(i915)) {
+		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+	}
+}
+
 /*
  * The workarounds in this function apply to shared registers in
  * the general render reset domain that aren't tied to a
@@ -2690,14 +2709,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_PONTEVECCHIO(i915)) {
-		/*
-		 * The following is not actually a "workaround" but rather
-		 * a recommended tuning setting documented in the bspec's
-		 * performance guide section.
-		 */
-		wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+	add_render_compute_tuning_settings(i915, wal);
 
+	if (IS_PONTEVECCHIO(i915)) {
 		/* Wa_16016694945 */
 		wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
 	}
-- 
2.37.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dg2: Add additional tuning settings
@ 2022-08-15 22:42 Lucas De Marchi
  2022-08-15 23:46 ` [Intel-gfx] [PATCH v2 " Matt Roper
  0 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2022-08-15 22:42 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, Aug 12, 2022 at 01:22:40PM -0700, Matt Roper wrote:
>Some additional MMIO tuning settings have appeared in the bspec's
>performance tuning guide section.
>
>One of the tuning settings here is also documented as formal workaround
>Wa_22012654132 for some steppings of DG2.  However the tuning setting
>applies to all DG2 variants and steppings, making it a superset of the
>workaround.
>
>Bspec: 68331
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  8 ++++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++++++++++++++-------
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index b3b49f6d6d1c..f64fafe28f72 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -259,6 +259,9 @@
> #define   GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
> #define   GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
>
>+#define DRAW_WATERMARK				_MMIO(0x26c0)
>+#define   VERT_WM_VAL				REG_GENMASK(9, 0)
>+
> #define GEN12_GLOBAL_MOCS(i)			_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
>
> #define RENDER_HWS_PGA_GEN7			_MMIO(0x4080)
>@@ -374,6 +377,9 @@
> #define CHICKEN_RASTER_1			_MMIO(0x6204)
> #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>
>+#define CHICKEN_RASTER_2			_MMIO(0x6208)
>+#define   TBIMR_FAST_CLIP			REG_BIT(5)
>+
> #define VFLSKPD					_MMIO(0x62a8)
> #define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
> #define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
>@@ -1124,6 +1130,8 @@
>
> #define RT_CTRL					_MMIO(0xe530)
> #define   DIS_NULL_QUERY			REG_BIT(10)
>+#define   STACKID_CTRL				REG_GENMASK(6, 5)
>+#define   STACKID_CTRL_512			REG_FIELD_PREP(STACKID_CTRL, 0x2)
>
> #define EU_PERF_CNTL1				_MMIO(0xe558)
> #define EU_PERF_CNTL5				_MMIO(0xe55c)
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index a68d279b01f0..2db7f7dc3c8c 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -568,6 +568,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> 				   struct i915_wa_list *wal)
> {
>+	wa_write_or(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);

this is a masked register

>+	wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
>+			 REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));

I don't see 26C0 in the context image... should this be
in engine_fake_wa_init() ?

Lucas De Marchi

> 	wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> 			 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> 	wa_add(wal,
>@@ -2195,15 +2198,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> 		wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
> 	}
>
>-	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
>-	    IS_DG2_G11(i915)) {
>-		/* Wa_22012654132:dg2 */
>-		wa_add(wal, GEN10_CACHE_MODE_SS, 0,
>-		       _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
>-		       0 /* write-only, so skip validation */,
>-		       true);
>-	}
>-
> 	/* Wa_14013202645:dg2 */
> 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
> 	    IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
>@@ -2692,6 +2686,21 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
>
> 	if (IS_DG2(i915)) {
> 		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>+		wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>+
>+		/*
>+		 * This is also listed as Wa_22012654132 for certain DG2
>+		 * steppings, but the tuning setting programming is a superset
>+		 * since it applies to all DG2 variants and steppings.
>+		 *
>+		 * Note that register 0xE420 is write-only and cannot be read
>+		 * back for verification on DG2 (due to Wa_14012342262), so
>+		 * we need to explicitly skip the readback.
>+		 */
>+		wa_add(wal, GEN10_CACHE_MODE_SS, 0,
>+		       _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
>+		       0 /* write-only, so skip validation */,
>+		       true);
> 	}
> }
>
>-- 
>2.37.1
>

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-08-24 18:03 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-08-16 21:06 [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings Matt Roper
2022-08-16 21:06 ` Matt Roper
2022-08-16 21:06 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/dg2: Add additional " Matt Roper
2022-08-16 21:06   ` Matt Roper
2022-08-17  5:19   ` [Intel-gfx] " Lucas De Marchi
2022-08-16 21:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/gt: Add dedicated function for non-ctx register " Patchwork
2022-08-16 23:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-17  5:57   ` Matt Roper
  -- strict thread matches above, loose matches on Subject: below --
2022-08-15 22:42 [Intel-gfx] [PATCH 2/2] drm/i915/dg2: Add additional " Lucas De Marchi
2022-08-15 23:46 ` [Intel-gfx] [PATCH v2 " Matt Roper

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