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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Kristina Martsenko <kristina.martsenko@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 14/28] arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1.AdvSIMD constants
Date: Thu, 18 Aug 2022 13:24:11 +0100	[thread overview]
Message-ID: <20220818122425.37889-15-broonie@kernel.org> (raw)
In-Reply-To: <20220818122425.37889-1-broonie@kernel.org>

The architecture refers to the register field identifying advanced SIMD as
AdvSIMD but the kernel refers to it as ASIMD. Use the architecture's
naming. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h                | 4 ++--
 arch/arm64/kernel/cpufeature.c                 | 6 +++---
 arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +-
 arch/arm64/kvm/hyp/nvhe/pkvm.c                 | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f123d73db3c5..b264ed35373b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -695,7 +695,7 @@
 #define ID_AA64PFR0_EL1_SVE_SHIFT		32
 #define ID_AA64PFR0_EL1_RAS_SHIFT		28
 #define ID_AA64PFR0_EL1_GIC_SHIFT		24
-#define ID_AA64PFR0_EL1_ASIMD_SHIFT		20
+#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT		20
 #define ID_AA64PFR0_EL1_FP_SHIFT		16
 #define ID_AA64PFR0_EL1_EL3_SHIFT		12
 #define ID_AA64PFR0_EL1_EL2_SHIFT		8
@@ -708,7 +708,7 @@
 #define ID_AA64PFR0_EL1_RAS_V1P1		0x2
 #define ID_AA64PFR0_EL1_FP_NI			0xf
 #define ID_AA64PFR0_EL1_FP_IMP			0x0
-#define ID_AA64PFR0_EL1_ASIMD_NI		0xf
+#define ID_AA64PFR0_EL1_AdvSIMD_NI		0xf
 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
 
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 4f82aad686eb..4e2444da67b1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -253,7 +253,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 				   FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
-	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, ID_AA64PFR0_EL1_ASIMD_NI),
+	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
@@ -2707,8 +2707,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
-	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
-	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
+	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
+	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 6200d53600ba..07edfc7524c9 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -36,7 +36,7 @@
  */
 #define PVM_ID_AA64PFR0_ALLOW (\
 	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \
-	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_ASIMD) | \
+	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \
 	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \
 	)
 
diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index b92ecdd6bdab..fc3e32709ba2 100644
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -31,7 +31,7 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
 	 */
 	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP),
 				PVM_ID_AA64PFR0_ALLOW));
-	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_ASIMD),
+	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD),
 				PVM_ID_AA64PFR0_ALLOW));
 
 	/* Trap RAS unless all current versions are supported */
-- 
2.30.2


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  parent reply	other threads:[~2022-08-18 12:39 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-18 12:23 [PATCH v4 00/28] arm64/sysreg: More system register generation Mark Brown
2022-08-18 12:23 ` [PATCH v4 01/28] arm64/sysreg: Remove stray SMIDR_EL1 defines Mark Brown
2022-08-18 12:23 ` [PATCH v4 02/28] arm64/sysreg: Describe ID_AA64SMFR0_EL1.SMEVer as an enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 03/28] arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK Mark Brown
2022-08-18 12:24 ` [PATCH v4 04/28] arm64/sysreg: Add _EL1 into ID_AA64MMFR0_EL1 definition names Mark Brown
2022-08-18 12:24 ` [PATCH v4 05/28] arm64/sysreg: Add _EL1 into ID_AA64MMFR2_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 06/28] arm64/sysreg: Add _EL1 into ID_AA64PFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 07/28] arm64/sysreg: Add _EL1 into ID_AA64PFR1_EL1 constant names Mark Brown
2022-08-18 12:24 ` [PATCH v4 08/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.BigEnd Mark Brown
2022-08-18 12:24 ` [PATCH v4 09/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits Mark Brown
2022-08-18 12:24 ` [PATCH v4 10/28] arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields Mark Brown
2022-08-18 12:24 ` [PATCH v4 11/28] arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.VARange Mark Brown
2022-08-18 12:24 ` [PATCH v4 12/28] arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.CnP Mark Brown
2022-08-18 12:24 ` [PATCH v4 13/28] arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1 constants Mark Brown
2022-08-18 12:24 ` Mark Brown [this message]
2022-08-18 12:24 ` [PATCH v4 15/28] arm64/sysreg: Standardise naming for SSBS feature enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 16/28] arm64/sysreg: Standardise naming for MTE " Mark Brown
2022-08-18 12:24 ` [PATCH v4 17/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 fractional version fields Mark Brown
2022-08-18 12:24 ` [PATCH v4 18/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 BTI enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 19/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 SME enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 20/28] arm64/sysreg: Convert HCRX_EL2 to automatic generation Mark Brown
2022-08-18 12:24 ` [PATCH v4 21/28] arm64/sysreg: Convert ID_AA64MMFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 22/28] arm64/sysreg: Convert ID_AA64MMFR1_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 23/28] arm64/sysreg: Convert ID_AA64MMFR2_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 24/28] arm64/sysreg: Convert ID_AA64PFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 25/28] arm64/sysreg: Convert ID_AA64PFR1_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 26/28] arm64/sysreg: Convert TIPDR_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 27/28] arm64/sysreg: Convert SCXTNUM_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 28/28] arm64/sysreg: Add defintion for ALLINT Mark Brown

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