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From: Rob Herring <robh@kernel.org>
To: Conor.Dooley@microchip.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	mturquette@baylibre.com, linux-riscv@lists.infradead.org,
	palmer@dabbelt.com, sboyd@kernel.org, aou@eecs.berkeley.edu,
	Hugh.Breslin@microchip.com, krzysztof.kozlowski+dt@linaro.org,
	paul.walmsley@sifive.com, linux-clk@vger.kernel.org,
	Daire.McNamara@microchip.com
Subject: Re: [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks
Date: Mon, 22 Aug 2022 16:53:49 -0500	[thread overview]
Message-ID: <20220822215349.GA913400-robh@kernel.org> (raw)
In-Reply-To: <92e15fa9-65f4-1dea-48eb-f3afbea5d3f4@microchip.com>

On Mon, Aug 22, 2022 at 07:44:20PM +0000, Conor.Dooley@microchip.com wrote:
> On 22/08/2022 20:40, Rob Herring wrote:
> > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote:
> >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> >> ordinal corners of the chip, which our documentation refers to as
> >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> >> highly configurable & many of the input clocks are optional.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >>  .../bindings/clock/microchip,mpfs-ccc.yaml    | 81 +++++++++++++++++++
> >>  1 file changed, 81 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> >>
> > 
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> Heh, been waiting for this one all day. Messed up squashing commits
> before sending v2... fixed locally & I'll respin later in the week.
> I tried to mark it "changes required" in patchwork so you'd not waste
> time on it but I think that got reverted?

Could have. The CI job messes with the state and then I do, and my 
scripts don't expect the state changing underneath it. Most users don't 
have PW accounts.

Don't worry, I don't spend much time on failing patches.

Rob

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Conor.Dooley@microchip.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	mturquette@baylibre.com, linux-riscv@lists.infradead.org,
	palmer@dabbelt.com, sboyd@kernel.org, aou@eecs.berkeley.edu,
	Hugh.Breslin@microchip.com, krzysztof.kozlowski+dt@linaro.org,
	paul.walmsley@sifive.com, linux-clk@vger.kernel.org,
	Daire.McNamara@microchip.com
Subject: Re: [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks
Date: Mon, 22 Aug 2022 16:53:49 -0500	[thread overview]
Message-ID: <20220822215349.GA913400-robh@kernel.org> (raw)
In-Reply-To: <92e15fa9-65f4-1dea-48eb-f3afbea5d3f4@microchip.com>

On Mon, Aug 22, 2022 at 07:44:20PM +0000, Conor.Dooley@microchip.com wrote:
> On 22/08/2022 20:40, Rob Herring wrote:
> > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote:
> >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> >> ordinal corners of the chip, which our documentation refers to as
> >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> >> highly configurable & many of the input clocks are optional.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >>  .../bindings/clock/microchip,mpfs-ccc.yaml    | 81 +++++++++++++++++++
> >>  1 file changed, 81 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> >>
> > 
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> Heh, been waiting for this one all day. Messed up squashing commits
> before sending v2... fixed locally & I'll respin later in the week.
> I tried to mark it "changes required" in patchwork so you'd not waste
> time on it but I think that got reverted?

Could have. The CI job messes with the state and then I do, and my 
scripts don't expect the state changing underneath it. Most users don't 
have PW accounts.

Don't worry, I don't spend much time on failing patches.

Rob

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-08-22 21:54 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-22 11:29 [PATCH v2 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Conor Dooley
2022-08-22 11:29 ` Conor Dooley
2022-08-22 11:29 ` [PATCH v2 1/6] dt-bindings: clk: rename mpfs-clkcfg binding Conor Dooley
2022-08-22 11:29   ` Conor Dooley
2022-08-22 11:29 ` [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks Conor Dooley
2022-08-22 11:29   ` Conor Dooley
2022-08-22 11:53   ` Conor.Dooley
2022-08-22 11:53     ` Conor.Dooley
2022-08-22 19:40   ` Rob Herring
2022-08-22 19:40     ` Rob Herring
2022-08-22 19:44     ` Conor.Dooley
2022-08-22 19:44       ` Conor.Dooley
2022-08-22 21:53       ` Rob Herring [this message]
2022-08-22 21:53         ` Rob Herring
2022-08-22 11:29 ` [PATCH v2 3/6] dt-bindings: clk: add PolarFire SoC fabric clock ids Conor Dooley
2022-08-22 11:29   ` Conor Dooley
2022-08-22 11:29 ` [PATCH v2 4/6] clk: microchip: add PolarFire SoC fabric clock support Conor Dooley
2022-08-22 11:29   ` Conor Dooley
2022-08-22 11:29 ` [PATCH v2 5/6] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-22 11:29   ` Conor Dooley
2022-08-22 11:29 ` [PATCH v2 6/6] riscv: dts: microchip: add the mpfs' fabric clock control Conor Dooley
2022-08-22 11:29   ` Conor Dooley

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