From: Jisheng Zhang <jszhang@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v2 0/5] riscv: add PREEMPT_RT support
Date: Thu, 1 Sep 2022 01:59:15 +0800 [thread overview]
Message-ID: <20220831175920.2806-1-jszhang@kernel.org> (raw)
This series is to add PREEMPT_RT support to riscv:
patch1 adds the missing number of signal exits in vCPU stat
patch2 switches to the generic guest entry infrastructure
patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for
RT
patch4 adds lazy preempt support
patch5 allows to enable PREEMPT_RT
I assume patch1, patch2 and patch3 can be reviewed and merged for
riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree,
and finally merged once the remaining patches in rt tree are all
mainlined.
Since v1:
- send to related maillist, I press ENTER too quickly when sending v1
- remove the signal_pending() handling because that's covered by
generic guest entry infrastructure
Jisheng Zhang (5):
RISC-V: KVM: Record number of signal exits as a vCPU stat
RISC-V: KVM: Use generic guest entry infrastructure
riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
riscv: add lazy preempt support
riscv: Allow to enable RT
arch/riscv/Kconfig | 3 +++
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/include/asm/thread_info.h | 7 +++++--
arch/riscv/kernel/asm-offsets.c | 1 +
arch/riscv/kernel/entry.S | 9 +++++++--
arch/riscv/kvm/Kconfig | 1 +
arch/riscv/kvm/vcpu.c | 18 +++++++-----------
7 files changed, 25 insertions(+), 15 deletions(-)
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
Thomas Gleixner <tglx@linutronix.de>,
Steven Rostedt <rostedt@goodmis.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v2 0/5] riscv: add PREEMPT_RT support
Date: Thu, 1 Sep 2022 01:59:15 +0800 [thread overview]
Message-ID: <20220831175920.2806-1-jszhang@kernel.org> (raw)
This series is to add PREEMPT_RT support to riscv:
patch1 adds the missing number of signal exits in vCPU stat
patch2 switches to the generic guest entry infrastructure
patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for
RT
patch4 adds lazy preempt support
patch5 allows to enable PREEMPT_RT
I assume patch1, patch2 and patch3 can be reviewed and merged for
riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree,
and finally merged once the remaining patches in rt tree are all
mainlined.
Since v1:
- send to related maillist, I press ENTER too quickly when sending v1
- remove the signal_pending() handling because that's covered by
generic guest entry infrastructure
Jisheng Zhang (5):
RISC-V: KVM: Record number of signal exits as a vCPU stat
RISC-V: KVM: Use generic guest entry infrastructure
riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
riscv: add lazy preempt support
riscv: Allow to enable RT
arch/riscv/Kconfig | 3 +++
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/include/asm/thread_info.h | 7 +++++--
arch/riscv/kernel/asm-offsets.c | 1 +
arch/riscv/kernel/entry.S | 9 +++++++--
arch/riscv/kvm/Kconfig | 1 +
arch/riscv/kvm/vcpu.c | 18 +++++++-----------
7 files changed, 25 insertions(+), 15 deletions(-)
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
Thomas Gleixner <tglx@linutronix.de>,
Steven Rostedt <rostedt@goodmis.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v2 0/5] riscv: add PREEMPT_RT support
Date: Thu, 1 Sep 2022 01:59:15 +0800 [thread overview]
Message-ID: <20220831175920.2806-1-jszhang@kernel.org> (raw)
This series is to add PREEMPT_RT support to riscv:
patch1 adds the missing number of signal exits in vCPU stat
patch2 switches to the generic guest entry infrastructure
patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for
RT
patch4 adds lazy preempt support
patch5 allows to enable PREEMPT_RT
I assume patch1, patch2 and patch3 can be reviewed and merged for
riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree,
and finally merged once the remaining patches in rt tree are all
mainlined.
Since v1:
- send to related maillist, I press ENTER too quickly when sending v1
- remove the signal_pending() handling because that's covered by
generic guest entry infrastructure
Jisheng Zhang (5):
RISC-V: KVM: Record number of signal exits as a vCPU stat
RISC-V: KVM: Use generic guest entry infrastructure
riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
riscv: add lazy preempt support
riscv: Allow to enable RT
arch/riscv/Kconfig | 3 +++
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/include/asm/thread_info.h | 7 +++++--
arch/riscv/kernel/asm-offsets.c | 1 +
arch/riscv/kernel/entry.S | 9 +++++++--
arch/riscv/kvm/Kconfig | 1 +
arch/riscv/kvm/vcpu.c | 18 +++++++-----------
7 files changed, 25 insertions(+), 15 deletions(-)
--
2.34.1
next reply other threads:[~2022-08-31 17:59 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 17:59 Jisheng Zhang [this message]
2022-08-31 17:59 ` [PATCH v2 0/5] riscv: add PREEMPT_RT support Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 4/5] riscv: add lazy preempt support Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-09-04 15:16 ` Guo Ren
2022-09-04 15:16 ` Guo Ren
2022-09-04 15:16 ` Guo Ren
2022-09-05 6:34 ` Sebastian Andrzej Siewior
2022-09-05 6:34 ` Sebastian Andrzej Siewior
2022-09-05 6:34 ` Sebastian Andrzej Siewior
2022-09-05 8:33 ` Guo Ren
2022-09-05 8:33 ` Guo Ren
2022-09-05 8:33 ` Guo Ren
2022-09-05 8:46 ` Sebastian Andrzej Siewior
2022-09-05 8:46 ` Sebastian Andrzej Siewior
2022-09-05 8:46 ` Sebastian Andrzej Siewior
2022-09-06 1:46 ` Guo Ren
2022-09-06 1:46 ` Guo Ren
2022-09-06 1:46 ` Guo Ren
2022-09-05 12:58 ` Jisheng Zhang
2022-09-05 12:58 ` Jisheng Zhang
2022-09-05 12:58 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 5/5] riscv: Allow to enable RT Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-08-31 17:59 ` Jisheng Zhang
2022-09-01 7:04 ` [PATCH v2 0/5] riscv: add PREEMPT_RT support Sebastian Andrzej Siewior
2022-09-01 7:04 ` Sebastian Andrzej Siewior
2022-09-01 7:04 ` Sebastian Andrzej Siewior
2022-09-01 13:44 ` Jisheng Zhang
2022-09-01 13:44 ` Jisheng Zhang
2022-09-01 13:44 ` Jisheng Zhang
2022-09-01 16:41 ` Conor.Dooley
2022-09-01 16:41 ` Conor.Dooley
2022-09-01 16:41 ` Conor.Dooley
2022-09-02 13:09 ` Jisheng Zhang
2022-09-02 13:09 ` Jisheng Zhang
2022-09-02 13:09 ` Jisheng Zhang
2022-09-02 13:29 ` Conor.Dooley
2022-09-02 13:29 ` Conor.Dooley
2022-09-02 13:29 ` Conor.Dooley
2022-11-11 14:32 ` Sebastian Andrzej Siewior
2022-11-11 14:32 ` Sebastian Andrzej Siewior
2022-11-11 14:32 ` Sebastian Andrzej Siewior
2022-11-11 14:34 ` Conor.Dooley
2022-11-11 14:34 ` Conor.Dooley
2022-11-11 14:34 ` Conor.Dooley
2022-11-12 21:40 ` Conor.Dooley
2022-11-12 21:40 ` Conor.Dooley
2022-11-12 21:40 ` Conor.Dooley
2023-03-14 13:07 ` Schaffner, Tobias
2023-03-14 13:07 ` Schaffner, Tobias
2023-03-14 13:07 ` Schaffner, Tobias
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220831175920.2806-1-jszhang@kernel.org \
--to=jszhang@kernel.org \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.