From: Jakub Kicinski <kuba@kernel.org>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: davem@davemloft.net, Rob Herring <robh+dt@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
thomas.petazzoni@bootlin.com, Andrew Lunn <andrew@lunn.ch>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v3 4/5] net: altera: tse: convert to phylink
Date: Thu, 1 Sep 2022 21:10:21 -0700 [thread overview]
Message-ID: <20220901211021.52520588@kernel.org> (raw)
In-Reply-To: <20220901143543.416977-5-maxime.chevallier@bootlin.com>
On Thu, 1 Sep 2022 16:35:42 +0200 Maxime Chevallier wrote:
> This commit converts the Altera Triple Speed Ethernet Controller to
> phylink. This controller supports MII, GMII and RGMII with its MAC, and
> SGMII + 1000BaseX through a small embedded PCS.
>
> The PCS itself has a register set very similar to what is found in a
> typical 802.3 ethernet PHY, but this register set memory-mapped instead
> of lying on an mdio bus.
allmodconfig builds report:
ERROR: modpost: missing MODULE_LICENSE() in drivers/net/pcs/pcs-altera-tse.o
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WARNING: multiple messages have this Message-ID (diff)
From: Jakub Kicinski <kuba@kernel.org>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: davem@davemloft.net, Rob Herring <robh+dt@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
thomas.petazzoni@bootlin.com, Andrew Lunn <andrew@lunn.ch>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v3 4/5] net: altera: tse: convert to phylink
Date: Thu, 1 Sep 2022 21:10:21 -0700 [thread overview]
Message-ID: <20220901211021.52520588@kernel.org> (raw)
In-Reply-To: <20220901143543.416977-5-maxime.chevallier@bootlin.com>
On Thu, 1 Sep 2022 16:35:42 +0200 Maxime Chevallier wrote:
> This commit converts the Altera Triple Speed Ethernet Controller to
> phylink. This controller supports MII, GMII and RGMII with its MAC, and
> SGMII + 1000BaseX through a small embedded PCS.
>
> The PCS itself has a register set very similar to what is found in a
> typical 802.3 ethernet PHY, but this register set memory-mapped instead
> of lying on an mdio bus.
allmodconfig builds report:
ERROR: modpost: missing MODULE_LICENSE() in drivers/net/pcs/pcs-altera-tse.o
next prev parent reply other threads:[~2022-09-02 4:11 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 14:35 [PATCH net-next v3 0/5] net: altera: tse: phylink conversion Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 1/5] dt-bindings: net: Convert Altera TSE bindings to yaml Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 2/5] net: altera: tse: cosmetic change to use reverse xmas tree ordering Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 3/5] net: pcs: add new PCS driver for altera TSE PCS Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
2022-10-09 5:38 ` Sean Anderson
2022-10-09 5:38 ` Sean Anderson
2022-10-26 9:37 ` Maxime Chevallier
2022-10-26 9:37 ` Maxime Chevallier
2022-10-26 12:05 ` Andrew Lunn
2022-10-26 12:05 ` Andrew Lunn
2022-10-26 12:47 ` Russell King (Oracle)
2022-10-26 12:47 ` Russell King (Oracle)
2022-09-01 14:35 ` [PATCH net-next v3 4/5] net: altera: tse: convert to phylink Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
2022-09-02 4:10 ` Jakub Kicinski [this message]
2022-09-02 4:10 ` Jakub Kicinski
2022-09-02 7:57 ` Maxime Chevallier
2022-09-02 7:57 ` Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 5/5] dt-bindings: net: altera: tse: add an optional pcs register range Maxime Chevallier
2022-09-01 14:35 ` Maxime Chevallier
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