* [PATCH 0/9] accumulated dts updates for ls1046a
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree; +Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang
Hou Zhiqiang (1):
arm64: dts: ls1046a: Add big-endian property for PCIe nodes
Laurentiu Tudor (2):
arm64: dts: ls1046a: add missing dma ranges property
arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma
size
Li Yang (4):
arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
arm64: dts: ls1046a: make dma-coherent global to the SoC
arm64: dts: ls1046a: add gpios based i2c recovery information
arm64: dts: ls1046a-qds: add mmio based mdio-mux support
Pankaj Bansal (1):
arm64: dts: ls1046a-qds: Modify the qspi flash frequency
Xiaowei Bao (1):
arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 158 +++++++++++++++++-
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 112 ++++++++-----
2 files changed, 225 insertions(+), 45 deletions(-)
--
2.37.1
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Ran Wang
Enable USB3 HW LPM feature for ls1046a.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index feab604322cf..ddae3cb0a977 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -717,6 +717,7 @@ usb0: usb@2f00000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb1: usb@3000000 {
@@ -727,6 +728,7 @@ usb1: usb@3000000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb2: usb@3100000 {
@@ -737,6 +739,7 @@ usb2: usb@3100000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
sata: sata@3200000 {
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Ran Wang
Enable USB3 HW LPM feature for ls1046a.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index feab604322cf..ddae3cb0a977 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -717,6 +717,7 @@ usb0: usb@2f00000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb1: usb@3000000 {
@@ -727,6 +728,7 @@ usb1: usb@3000000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb2: usb@3100000 {
@@ -737,6 +739,7 @@ usb2: usb@3100000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
sata: sata@3200000 {
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Xiaowei Bao, Li Yang
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the PME interrupt property to the PCIe EP nodes.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ddae3cb0a977..fce3c6401653 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -813,6 +813,8 @@ pcie_ep1: pcie_ep@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
@@ -849,6 +851,8 @@ pcie_ep2: pcie_ep@3500000 {
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
@@ -885,6 +889,8 @@ pcie_ep3: pcie_ep@3600000 {
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Xiaowei Bao, Li Yang
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the PME interrupt property to the PCIe EP nodes.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ddae3cb0a977..fce3c6401653 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -813,6 +813,8 @@ pcie_ep1: pcie_ep@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
@@ -849,6 +851,8 @@ pcie_ep2: pcie_ep@3500000 {
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
@@ -885,6 +889,8 @@ pcie_ep3: pcie_ep@3600000 {
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
2022-08-24 23:11 ` Li Yang
@ 2022-09-05 1:10 ` Shawn Guo
-1 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:10 UTC (permalink / raw)
To: Li Yang; +Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel, Xiaowei Bao
On Wed, Aug 24, 2022 at 06:11:53PM -0500, Li Yang wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Add the PME interrupt property to the PCIe EP nodes.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index ddae3cb0a977..fce3c6401653 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -813,6 +813,8 @@ pcie_ep1: pcie_ep@3400000 {
> reg = <0x00 0x03400000 0x0 0x00100000>,
> <0x40 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
The comment seems unnecessary, considering we have the interrupt-names
below?
Shawn
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -849,6 +851,8 @@ pcie_ep2: pcie_ep@3500000 {
> reg = <0x00 0x03500000 0x0 0x00100000>,
> <0x48 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -885,6 +889,8 @@ pcie_ep3: pcie_ep@3600000 {
> reg = <0x00 0x03600000 0x0 0x00100000>,
> <0x50 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> --
> 2.37.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
@ 2022-09-05 1:10 ` Shawn Guo
0 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:10 UTC (permalink / raw)
To: Li Yang; +Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel, Xiaowei Bao
On Wed, Aug 24, 2022 at 06:11:53PM -0500, Li Yang wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Add the PME interrupt property to the PCIe EP nodes.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index ddae3cb0a977..fce3c6401653 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -813,6 +813,8 @@ pcie_ep1: pcie_ep@3400000 {
> reg = <0x00 0x03400000 0x0 0x00100000>,
> <0x40 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
The comment seems unnecessary, considering we have the interrupt-names
below?
Shawn
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -849,6 +851,8 @@ pcie_ep2: pcie_ep@3500000 {
> reg = <0x00 0x03500000 0x0 0x00100000>,
> <0x48 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -885,6 +889,8 @@ pcie_ep3: pcie_ep@3600000 {
> reg = <0x00 0x03600000 0x0 0x00100000>,
> <0x50 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Hou Zhiqiang, Li Yang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the big-endian property for LS1046A PCIe nodes for accessing PEX_LUT
and PF register block.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index fce3c6401653..f8e8c1415c02 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -805,6 +805,7 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -817,6 +818,7 @@ pcie_ep1: pcie_ep@3400000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -843,6 +845,7 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -855,6 +858,7 @@ pcie_ep2: pcie_ep@3500000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -881,6 +885,7 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -893,6 +898,7 @@ pcie_ep3: pcie_ep@3600000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Hou Zhiqiang, Li Yang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the big-endian property for LS1046A PCIe nodes for accessing PEX_LUT
and PF register block.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index fce3c6401653..f8e8c1415c02 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -805,6 +805,7 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -817,6 +818,7 @@ pcie_ep1: pcie_ep@3400000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -843,6 +845,7 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -855,6 +858,7 @@ pcie_ep2: pcie_ep@3500000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -881,6 +885,7 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -893,6 +898,7 @@ pcie_ep3: pcie_ep@3600000 {
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Laurentiu Tudor, Li Yang
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
ls1046a has a 48-bit address size so make sure that the dma-ranges
reflects this. Otherwise the linux kernel's dma sub-system will set the
default dma masks to full 64-bit, badly breaking dmas.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index f8e8c1415c02..552b4455aa82 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -272,6 +272,7 @@ soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Laurentiu Tudor, Li Yang
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
ls1046a has a 48-bit address size so make sure that the dma-ranges
reflects this. Otherwise the linux kernel's dma sub-system will set the
default dma masks to full 64-bit, badly breaking dmas.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index f8e8c1415c02..552b4455aa82 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -272,6 +272,7 @@ soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Laurentiu Tudor
ls1046a is really completely dma coherent in their entirety so add
the dma-coherent property at the soc level in the device tree.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 552b4455aa82..10b6c41570cc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Laurentiu Tudor
ls1046a is really completely dma coherent in their entirety so add
the dma-coherent property at the soc level in the device tree.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 552b4455aa82..10b6c41570cc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Laurentiu Tudor,
Robin Murphy, Li Yang
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Wrap the usb and sata controllers in an intermediate simple-bus and use
it to constrain the dma address size of these usb controllers to the 40
bits that they generate toward the interconnect. This is required
because the SoC uses 48 bits address sizes and this mismatch would lead
to smmu context faults because the usb generates 40-bit addresses while
the smmu page tables are populated with 48-bit wide addresses.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 90 ++++++++++---------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 10b6c41570cc..c7c6c82626fd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -711,47 +711,55 @@ QORIQ_CLK_PLL_DIV(2)>,
QORIQ_CLK_PLL_DIV(2)>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- sata: sata@3200000 {
- compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
- QORIQ_CLK_PLL_DIV(2)>;
+ aux_bus: aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
+
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
};
msi1: msi-controller@1580000 {
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Laurentiu Tudor,
Robin Murphy, Li Yang
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Wrap the usb and sata controllers in an intermediate simple-bus and use
it to constrain the dma address size of these usb controllers to the 40
bits that they generate toward the interconnect. This is required
because the SoC uses 48 bits address sizes and this mismatch would lead
to smmu context faults because the usb generates 40-bit addresses while
the smmu page tables are populated with 48-bit wide addresses.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 90 ++++++++++---------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 10b6c41570cc..c7c6c82626fd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -711,47 +711,55 @@ QORIQ_CLK_PLL_DIV(2)>,
QORIQ_CLK_PLL_DIV(2)>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- sata: sata@3200000 {
- compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
- QORIQ_CLK_PLL_DIV(2)>;
+ aux_bus: aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
+
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
};
msi1: msi-controller@1580000 {
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Zhang Ying
Add scl-gpios property for i2c recovery and add SoC specific compatible
string for SoC specific fixup.
Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index c7c6c82626fd..c95a990e2edd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -502,7 +502,7 @@ dspi: spi@2100000 {
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -516,35 +516,38 @@ i2c0: i2c@2180000 {
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 2 0>;
status = "disabled";
};
i2c2: i2c@21a0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 10 0>;
status = "disabled";
};
i2c3: i2c@21b0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Zhang Ying
Add scl-gpios property for i2c recovery and add SoC specific compatible
string for SoC specific fixup.
Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index c7c6c82626fd..c95a990e2edd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -502,7 +502,7 @@ dspi: spi@2100000 {
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -516,35 +516,38 @@ i2c0: i2c@2180000 {
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 2 0>;
status = "disabled";
};
i2c2: i2c@21a0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 10 0>;
status = "disabled";
};
i2c3: i2c@21b0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information
2022-08-24 23:11 ` Li Yang
@ 2022-09-05 1:12 ` Shawn Guo
-1 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:12 UTC (permalink / raw)
To: Li Yang; +Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel, Zhang Ying
On Wed, Aug 24, 2022 at 06:11:58PM -0500, Li Yang wrote:
> Add scl-gpios property for i2c recovery and add SoC specific compatible
> string for SoC specific fixup.
>
> Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index c7c6c82626fd..c95a990e2edd 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -502,7 +502,7 @@ dspi: spi@2100000 {
> };
>
> i2c0: i2c@2180000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2180000 0x0 0x10000>;
> @@ -516,35 +516,38 @@ i2c0: i2c@2180000 {
> };
>
> i2c1: i2c@2190000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2190000 0x0 0x10000>;
> interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 2 0>;
Use define for polarity cell?
Shawn
> status = "disabled";
> };
>
> i2c2: i2c@21a0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21a0000 0x0 0x10000>;
> interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 10 0>;
> status = "disabled";
> };
>
> i2c3: i2c@21b0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21b0000 0x0 0x10000>;
> interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 12 0>;
> status = "disabled";
> };
>
> --
> 2.37.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information
@ 2022-09-05 1:12 ` Shawn Guo
0 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:12 UTC (permalink / raw)
To: Li Yang; +Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel, Zhang Ying
On Wed, Aug 24, 2022 at 06:11:58PM -0500, Li Yang wrote:
> Add scl-gpios property for i2c recovery and add SoC specific compatible
> string for SoC specific fixup.
>
> Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index c7c6c82626fd..c95a990e2edd 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -502,7 +502,7 @@ dspi: spi@2100000 {
> };
>
> i2c0: i2c@2180000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2180000 0x0 0x10000>;
> @@ -516,35 +516,38 @@ i2c0: i2c@2180000 {
> };
>
> i2c1: i2c@2190000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2190000 0x0 0x10000>;
> interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 2 0>;
Use define for polarity cell?
Shawn
> status = "disabled";
> };
>
> i2c2: i2c@21a0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21a0000 0x0 0x10000>;
> interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 10 0>;
> status = "disabled";
> };
>
> i2c3: i2c@21b0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21b0000 0x0 0x10000>;
> interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(2)>;
> + scl-gpios = <&gpio3 12 0>;
> status = "disabled";
> };
>
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:11 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Camelia Groza,
Pankaj Bansal
There is mmio based mdio mux function in the FPGA device on ls1046a-qds
board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++-
1 file changed, 154 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index eec62c63dafe..eb74ed6419b6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@@ -25,6 +25,20 @@ aliases {
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+
+ emi1-slot1 = &ls1046mdio_s1;
+ emi1-slot2 = &ls1046mdio_s2;
+ emi1-slot4 = &ls1046mdio_s4;
+
+ sgmii-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-s1-p2 = &sgmii_phy_s1_p2;
+ sgmii-s1-p3 = &sgmii_phy_s1_p3;
+ sgmii-s1-p4 = &sgmii_phy_s1_p4;
+ sgmii-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
};
chosen {
@@ -153,8 +167,9 @@ nand@1,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0 2 0 0x100>;
};
};
@@ -177,3 +192,140 @@ qflash0: flash@0 {
};
#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&sgmii_phy_s4_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy_s1_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy_s1_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ phy-handle = <&sgmii_phy_s1_p1>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* DTSEC10/10GEC2 */
+ phy-handle = <&sgmii_phy_s1_p2>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mdio-mux-emi1@54 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1046mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1046mdio1: mdio@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1046mdio_s1: mdio@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ sgmii_phy_s1_p2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy_s1_p3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy_s1_p4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1046mdio_s2: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1046mdio_s4: mdio@80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support
@ 2022-08-24 23:11 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:11 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Li Yang, Camelia Groza,
Pankaj Bansal
There is mmio based mdio mux function in the FPGA device on ls1046a-qds
board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++-
1 file changed, 154 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index eec62c63dafe..eb74ed6419b6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@@ -25,6 +25,20 @@ aliases {
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+
+ emi1-slot1 = &ls1046mdio_s1;
+ emi1-slot2 = &ls1046mdio_s2;
+ emi1-slot4 = &ls1046mdio_s4;
+
+ sgmii-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-s1-p2 = &sgmii_phy_s1_p2;
+ sgmii-s1-p3 = &sgmii_phy_s1_p3;
+ sgmii-s1-p4 = &sgmii_phy_s1_p4;
+ sgmii-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
};
chosen {
@@ -153,8 +167,9 @@ nand@1,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0 2 0 0x100>;
};
};
@@ -177,3 +192,140 @@ qflash0: flash@0 {
};
#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&sgmii_phy_s4_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy_s1_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy_s1_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ phy-handle = <&sgmii_phy_s1_p1>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* DTSEC10/10GEC2 */
+ phy-handle = <&sgmii_phy_s1_p2>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mdio-mux-emi1@54 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1046mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1046mdio1: mdio@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1046mdio_s1: mdio@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ sgmii_phy_s1_p2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy_s1_p3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy_s1_p4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1046mdio_s2: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1046mdio_s4: mdio@80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support
2022-08-24 23:11 ` Li Yang
@ 2022-09-05 1:17 ` Shawn Guo
-1 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:17 UTC (permalink / raw)
To: Li Yang
Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel,
Camelia Groza, Pankaj Bansal
On Wed, Aug 24, 2022 at 06:11:59PM -0500, Li Yang wrote:
> There is mmio based mdio mux function in the FPGA device on ls1046a-qds
> board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and
> add simple-mfd as a compatbile for the FPGA node to reflect the
> multi-function nature of it.
>
> Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++-
> 1 file changed, 154 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> index eec62c63dafe..eb74ed6419b6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> @@ -3,7 +3,7 @@
> * Device Tree Include file for Freescale Layerscape-1046A family SoC.
> *
> * Copyright 2016 Freescale Semiconductor, Inc.
> - * Copyright 2018 NXP
> + * Copyright 2018-2021 NXP
> *
> * Shaohui Xie <Shaohui.Xie@nxp.com>
> */
> @@ -25,6 +25,20 @@ aliases {
> serial1 = &duart1;
> serial2 = &duart2;
> serial3 = &duart3;
> +
Unnecessary newline.
> + emi1-slot1 = &ls1046mdio_s1;
> + emi1-slot2 = &ls1046mdio_s2;
> + emi1-slot4 = &ls1046mdio_s4;
Keep the list alphabetically sorted?
> +
> + sgmii-s1-p1 = &sgmii_phy_s1_p1;
> + sgmii-s1-p2 = &sgmii_phy_s1_p2;
> + sgmii-s1-p3 = &sgmii_phy_s1_p3;
> + sgmii-s1-p4 = &sgmii_phy_s1_p4;
> + sgmii-s4-p1 = &sgmii_phy_s4_p1;
> + qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
> + qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
> + qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
> + qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
> };
>
> chosen {
> @@ -153,8 +167,9 @@ nand@1,0 {
> };
>
> fpga: board-control@2,0 {
> - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
> + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
> reg = <0x2 0x0 0x0000100>;
> + ranges = <0 2 0 0x100>;
> };
> };
>
> @@ -177,3 +192,140 @@ qflash0: flash@0 {
> };
>
> #include "fsl-ls1046-post.dtsi"
> +
> +&fman0 {
> + ethernet@e0000 {
> + phy-handle = <&qsgmii_phy_s2_p1>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@e2000 {
> + phy-handle = <&sgmii_phy_s4_p1>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@e4000 {
> + phy-handle = <&rgmii_phy1>;
> + phy-connection-type = "rgmii";
> + };
> +
> + ethernet@e6000 {
> + phy-handle = <&rgmii_phy2>;
> + phy-connection-type = "rgmii";
> + };
> +
> + ethernet@e8000 {
> + phy-handle = <&sgmii_phy_s1_p3>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@ea000 {
> + phy-handle = <&sgmii_phy_s1_p4>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@f0000 { /* DTSEC9/10GEC1 */
> + phy-handle = <&sgmii_phy_s1_p1>;
> + phy-connection-type = "xgmii";
> + };
> +
> + ethernet@f2000 { /* DTSEC10/10GEC2 */
> + phy-handle = <&sgmii_phy_s1_p2>;
> + phy-connection-type = "xgmii";
> + };
> +};
> +
> +&fpga {
> + #address-cells = <1>;
> + #size-cells = <1>;
Have a newline between properties and child node.
Shawn
> + mdio-mux-emi1@54 {
> + compatible = "mdio-mux-mmioreg", "mdio-mux";
> + mdio-parent-bus = <&mdio0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x54 1>; /* BRDCFG4 */
> + mux-mask = <0xe0>; /* EMI1 */
> +
> + /* On-board RGMII1 PHY */
> + ls1046mdio0: mdio@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
> + reg = <0x1>;
> + };
> + };
> +
> + /* On-board RGMII2 PHY */
> + ls1046mdio1: mdio@20 {
> + reg = <0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
> + reg = <0x2>;
> + };
> + };
> +
> + /* Slot 1 */
> + ls1046mdio_s1: mdio@40 {
> + reg = <0x40>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgmii_phy_s1_p1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + sgmii_phy_s1_p2: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + sgmii_phy_s1_p3: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + sgmii_phy_s1_p4: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> +
> + /* Slot 2 */
> + ls1046mdio_s2: mdio@60 {
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + qsgmii_phy_s2_p1: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + qsgmii_phy_s2_p2: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + qsgmii_phy_s2_p3: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + qsgmii_phy_s2_p4: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> +
> + /* Slot 4 */
> + ls1046mdio_s4: mdio@80 {
> + reg = <0x80>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgmii_phy_s4_p1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> + };
> + };
> +};
> --
> 2.37.1
>
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support
@ 2022-09-05 1:17 ` Shawn Guo
0 siblings, 0 replies; 26+ messages in thread
From: Shawn Guo @ 2022-09-05 1:17 UTC (permalink / raw)
To: Li Yang
Cc: devicetree, robh+dt, linux-arm-kernel, linux-kernel,
Camelia Groza, Pankaj Bansal
On Wed, Aug 24, 2022 at 06:11:59PM -0500, Li Yang wrote:
> There is mmio based mdio mux function in the FPGA device on ls1046a-qds
> board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and
> add simple-mfd as a compatbile for the FPGA node to reflect the
> multi-function nature of it.
>
> Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++-
> 1 file changed, 154 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> index eec62c63dafe..eb74ed6419b6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> @@ -3,7 +3,7 @@
> * Device Tree Include file for Freescale Layerscape-1046A family SoC.
> *
> * Copyright 2016 Freescale Semiconductor, Inc.
> - * Copyright 2018 NXP
> + * Copyright 2018-2021 NXP
> *
> * Shaohui Xie <Shaohui.Xie@nxp.com>
> */
> @@ -25,6 +25,20 @@ aliases {
> serial1 = &duart1;
> serial2 = &duart2;
> serial3 = &duart3;
> +
Unnecessary newline.
> + emi1-slot1 = &ls1046mdio_s1;
> + emi1-slot2 = &ls1046mdio_s2;
> + emi1-slot4 = &ls1046mdio_s4;
Keep the list alphabetically sorted?
> +
> + sgmii-s1-p1 = &sgmii_phy_s1_p1;
> + sgmii-s1-p2 = &sgmii_phy_s1_p2;
> + sgmii-s1-p3 = &sgmii_phy_s1_p3;
> + sgmii-s1-p4 = &sgmii_phy_s1_p4;
> + sgmii-s4-p1 = &sgmii_phy_s4_p1;
> + qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
> + qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
> + qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
> + qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
> };
>
> chosen {
> @@ -153,8 +167,9 @@ nand@1,0 {
> };
>
> fpga: board-control@2,0 {
> - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
> + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
> reg = <0x2 0x0 0x0000100>;
> + ranges = <0 2 0 0x100>;
> };
> };
>
> @@ -177,3 +192,140 @@ qflash0: flash@0 {
> };
>
> #include "fsl-ls1046-post.dtsi"
> +
> +&fman0 {
> + ethernet@e0000 {
> + phy-handle = <&qsgmii_phy_s2_p1>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@e2000 {
> + phy-handle = <&sgmii_phy_s4_p1>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@e4000 {
> + phy-handle = <&rgmii_phy1>;
> + phy-connection-type = "rgmii";
> + };
> +
> + ethernet@e6000 {
> + phy-handle = <&rgmii_phy2>;
> + phy-connection-type = "rgmii";
> + };
> +
> + ethernet@e8000 {
> + phy-handle = <&sgmii_phy_s1_p3>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@ea000 {
> + phy-handle = <&sgmii_phy_s1_p4>;
> + phy-connection-type = "sgmii";
> + };
> +
> + ethernet@f0000 { /* DTSEC9/10GEC1 */
> + phy-handle = <&sgmii_phy_s1_p1>;
> + phy-connection-type = "xgmii";
> + };
> +
> + ethernet@f2000 { /* DTSEC10/10GEC2 */
> + phy-handle = <&sgmii_phy_s1_p2>;
> + phy-connection-type = "xgmii";
> + };
> +};
> +
> +&fpga {
> + #address-cells = <1>;
> + #size-cells = <1>;
Have a newline between properties and child node.
Shawn
> + mdio-mux-emi1@54 {
> + compatible = "mdio-mux-mmioreg", "mdio-mux";
> + mdio-parent-bus = <&mdio0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x54 1>; /* BRDCFG4 */
> + mux-mask = <0xe0>; /* EMI1 */
> +
> + /* On-board RGMII1 PHY */
> + ls1046mdio0: mdio@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
> + reg = <0x1>;
> + };
> + };
> +
> + /* On-board RGMII2 PHY */
> + ls1046mdio1: mdio@20 {
> + reg = <0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
> + reg = <0x2>;
> + };
> + };
> +
> + /* Slot 1 */
> + ls1046mdio_s1: mdio@40 {
> + reg = <0x40>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgmii_phy_s1_p1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + sgmii_phy_s1_p2: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + sgmii_phy_s1_p3: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + sgmii_phy_s1_p4: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> +
> + /* Slot 2 */
> + ls1046mdio_s2: mdio@60 {
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + qsgmii_phy_s2_p1: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + qsgmii_phy_s2_p2: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + qsgmii_phy_s2_p3: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + qsgmii_phy_s2_p4: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> +
> + /* Slot 4 */
> + ls1046mdio_s4: mdio@80 {
> + reg = <0x80>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgmii_phy_s4_p1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> + };
> + };
> +};
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency
2022-08-24 23:11 ` Li Yang
@ 2022-08-24 23:12 ` Li Yang
-1 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:12 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Pankaj Bansal, Li Yang
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The qspi flash in ls1046a QDS board can operate at 50MHz frequency.
Therefore, update the maximum supported freq in dts file.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index eb74ed6419b6..f72dc65c45cd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -184,7 +184,7 @@ qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
--
2.37.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency
@ 2022-08-24 23:12 ` Li Yang
0 siblings, 0 replies; 26+ messages in thread
From: Li Yang @ 2022-08-24 23:12 UTC (permalink / raw)
To: shawnguo, devicetree
Cc: robh+dt, linux-arm-kernel, linux-kernel, Pankaj Bansal, Li Yang
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The qspi flash in ls1046a QDS board can operate at 50MHz frequency.
Therefore, update the maximum supported freq in dts file.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index eb74ed6419b6..f72dc65c45cd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -184,7 +184,7 @@ qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
--
2.37.1
^ permalink raw reply related [flat|nested] 26+ messages in thread