[PATCH v3 0/3] Enable {fcpvd,vspd} on RZ/G2L SoC

[PATCH v3 0/3] Enable {fcpvd,vspd} on RZ/G2L SoC

[Biju Das]

This patch series aims to enable {fcpvd,vspd} on RZ/G2L SoC.

patch[3] depend upon [1] and [2].
    [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220831&id=17b5179ef6cd6430945c1da4174ceaf43c93cf1e
    [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220831&id=882bda188f691320a001c6adc738c4a7ec102a8d

v2->v3:
 * Updated the compatibles by replacing items->enum as
   it is just one item.
v1->v2:
 * Documented RZ/{G2,V2}L FCPVD bindings
 * Introduces new compatibles renesas,r9a07g0{44,54}-fcpvd
 * Added clock-names property
 * described clocks.
 * Updated SoC dtsi to reflect changes in bindings.

Biju Das (3):
  media: dt-bindings: media: renesas,fcp: Document RZ/{G2,V2}L FCPVD
    bindings
  arm64: dts: renesas: r9a07g044: Add fcpvd node
  arm64: dts: renesas: r9a07g044: Add vspd node

 .../bindings/media/renesas,fcp.yaml           | 45 ++++++++++++++++---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 25 +++++++++++
 2 files changed, 65 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH v3 1/3] media: dt-bindings: media: renesas,fcp: Document RZ/{G2,V2}L FCPVD bindings

[Biju Das]

Document FCPVD found in RZ/G2L alike SoCs. FCPVD block is similar to
FCP for VSP found on R-Car SoC's . It has 3 clocks compared to 1
clock on fcpv. Introduce new compatibles renesas,r9a07g044-fcpvd
for RZ/G2{L,LC} and renesas,r9a07g054-fcpvd for RZ/V2L to handle this
difference.

The 3 clocks are shared between du, vspd and fcpvd. No driver changes
are required as generic compatible string "renesas,fcpv" will be used
as a fallback.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Updated the compatibles by replacing items->enum as
   it is just one item.
v1->v2:
 * Documented RZ/{G2,V2}L FCPVD bindings
 * Introduces new compatibles renesas,r9a07g0{44,54}-fcpvd
 * Added clock-names property
 * described clocks.
---
 .../bindings/media/renesas,fcp.yaml           | 45 ++++++++++++++++---
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml
index 43f2fed8cd33..c6abe719881b 100644
--- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml
@@ -21,15 +21,22 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - renesas,fcpv # FCP for VSP
-      - renesas,fcpf # FCP for FDP
+    oneOf:
+      - enum:
+          - renesas,fcpv # FCP for VSP
+          - renesas,fcpf # FCP for FDP
+      - items:
+          - enum:
+              - renesas,r9a07g044-fcpvd # RZ/G2{L,LC}
+              - renesas,r9a07g054-fcpvd # RZ/V2L
+          - const: renesas,fcpv         # Generic FCP for VSP fallback
 
   reg:
     maxItems: 1
 
-  clocks:
-    maxItems: 1
+  clocks: true
+
+  clock-names: true
 
   iommus:
     maxItems: 1
@@ -49,6 +56,34 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g044-fcpvd
+              - renesas,r9a07g054-fcpvd
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Main clock
+            - description: Register access clock
+            - description: Video clock
+        clock-names:
+          items:
+            - const: aclk
+            - const: pclk
+            - const: vclk
+      required:
+        - clock-names
+    else:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names: false
+
 examples:
   # R8A7795 (R-Car H3) FCP for VSP-D1
   - |
-- 
2.25.1

Re: [PATCH v3 1/3] media: dt-bindings: media: renesas,fcp: Document RZ/{G2,V2}L FCPVD bindings

[Rob Herring]

On Fri, 02 Sep 2022 07:46:26 +0100, Biju Das wrote:
> Document FCPVD found in RZ/G2L alike SoCs. FCPVD block is similar to
> FCP for VSP found on R-Car SoC's . It has 3 clocks compared to 1
> clock on fcpv. Introduce new compatibles renesas,r9a07g044-fcpvd
> for RZ/G2{L,LC} and renesas,r9a07g054-fcpvd for RZ/V2L to handle this
> difference.
> 
> The 3 clocks are shared between du, vspd and fcpvd. No driver changes
> are required as generic compatible string "renesas,fcpv" will be used
> as a fallback.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * Updated the compatibles by replacing items->enum as
>    it is just one item.
> v1->v2:
>  * Documented RZ/{G2,V2}L FCPVD bindings
>  * Introduces new compatibles renesas,r9a07g0{44,54}-fcpvd
>  * Added clock-names property
>  * described clocks.
> ---
>  .../bindings/media/renesas,fcp.yaml           | 45 ++++++++++++++++---
>  1 file changed, 40 insertions(+), 5 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH v3 1/3] media: dt-bindings: media: renesas,fcp: Document RZ/{G2,V2}L FCPVD bindings

[Biju Das]

Hi All,

Gentle ping. Are we happy with this patch? Can we add this to mainline?

Cheers,
Biju

> Subject: Re: [PATCH v3 1/3] media: dt-bindings: media: renesas,fcp:
> Document RZ/{G2,V2}L FCPVD bindings
> 
> On Fri, 02 Sep 2022 07:46:26 +0100, Biju Das wrote:
> > Document FCPVD found in RZ/G2L alike SoCs. FCPVD block is similar to
> > FCP for VSP found on R-Car SoC's . It has 3 clocks compared to 1
> clock
> > on fcpv. Introduce new compatibles renesas,r9a07g044-fcpvd for
> > RZ/G2{L,LC} and renesas,r9a07g054-fcpvd for RZ/V2L to handle this
> > difference.
> >
> > The 3 clocks are shared between du, vspd and fcpvd. No driver
> changes
> > are required as generic compatible string "renesas,fcpv" will be
> used
> > as a fallback.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * Updated the compatibles by replacing items->enum as
> >    it is just one item.
> > v1->v2:
> >  * Documented RZ/{G2,V2}L FCPVD bindings
> >  * Introduces new compatibles renesas,r9a07g0{44,54}-fcpvd
> >  * Added clock-names property
> >  * described clocks.
> > ---
> >  .../bindings/media/renesas,fcp.yaml           | 45
> ++++++++++++++++---
> >  1 file changed, 40 insertions(+), 5 deletions(-)
> >
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v3 2/3] arm64: dts: renesas: r9a07g044: Add fcpvd node

[Biju Das]

Add fcpvd node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Updated compatibles
 * Added clock-names property.
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 3652e511160f..f271b96c033d 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -611,6 +611,18 @@ sbc: spi@10060000 {
 			status = "disabled";
 		};
 
+		fcpvd: fcp@10880000 {
+			compatible = "renesas,r9a07g044-fcpvd",
+				     "renesas,fcpv";
+			reg = <0 0x10880000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_LCDC_RESET_N>;
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g044-cpg";
 			reg = <0 0x11010000 0 0x10000>;
-- 
2.25.1

[PATCH v3 3/3] arm64: dts: renesas: r9a07g044: Add vspd node

[Biju Das]

Add vspd node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change.
 Note:
  * This patch depend upon [1] and [2] in the next
    [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220831&id=17b5179ef6cd6430945c1da4174ceaf43c93cf1e
    [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220831&id=882bda188f691320a001c6adc738c4a7ec102a8d
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index f271b96c033d..1fc4be8d4ac6 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -611,6 +611,19 @@ sbc: spi@10060000 {
 			status = "disabled";
 		};
 
+		vspd: vsp@10870000 {
+			compatible = "renesas,r9a07g044-vsp2";
+			reg = <0 0x10870000 0 0x10000>;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_LCDC_RESET_N>;
+			renesas,fcp = <&fcpvd>;
+		};
+
 		fcpvd: fcp@10880000 {
 			compatible = "renesas,r9a07g044-fcpvd",
 				     "renesas,fcpv";
-- 
2.25.1

RE: [PATCH v3 0/3] Enable {fcpvd,vspd} on RZ/G2L SoC

[Biju Das]

Hi all,

Gentle ping.

Cheers,
Biju


> Subject: [PATCH v3 0/3] Enable {fcpvd,vspd} on RZ/G2L SoC
> 
> This patch series aims to enable {fcpvd,vspd} on RZ/G2L SoC.
> 
> patch[3] depend upon [1] and [2].
> 
> v2->v3:
>  * Updated the compatibles by replacing items->enum as
>    it is just one item.
> v1->v2:
>  * Documented RZ/{G2,V2}L FCPVD bindings
>  * Introduces new compatibles renesas,r9a07g0{44,54}-fcpvd
>  * Added clock-names property
>  * described clocks.
>  * Updated SoC dtsi to reflect changes in bindings.
> 
> Biju Das (3):
>   media: dt-bindings: media: renesas,fcp: Document RZ/{G2,V2}L FCPVD
>     bindings
>   arm64: dts: renesas: r9a07g044: Add fcpvd node
>   arm64: dts: renesas: r9a07g044: Add vspd node
> 
>  .../bindings/media/renesas,fcp.yaml           | 45 ++++++++++++++++--
> -
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 25 +++++++++++
>  2 files changed, 65 insertions(+), 5 deletions(-)
> 
> --
> 2.25.1