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From: Rob Herring <robh@kernel.org>
To: daire.mcnamara@microchip.com
Cc: aou@eecs.berkeley.edu, bhelgaas@google.com,
	conor.dooley@microchip.com, devicetree@vger.kernel.org,
	krzysztof.kozlowski+dt@linaro.org, kw@linux.com,
	linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
	lpieralisi@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, cyril.jean@microchip.com,
	padmarao.begari@microchip.com, heinrich.schuchardt@canonical.com,
	david.abdurachmanov@gmail.com
Subject: Re: [PATCH v1 4/4] of: PCI: tidy up logging of ranges containing configuration space type
Date: Thu, 8 Sep 2022 15:59:57 -0500	[thread overview]
Message-ID: <20220908205957.GB3240357-robh@kernel.org> (raw)
In-Reply-To: <20220902142202.2437658-5-daire.mcnamara@microchip.com>

On Fri, Sep 02, 2022 at 03:22:02PM +0100, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> PCI ranges can contain addresses where phys.high part can have a type
> of 0, signifying 'configuration space'.  Change
> devm_of_pci_get_host_bridge_resources() to print 'CFG' instead of 'err'
> for a PCI range containing such a 'configuration space' type.

Generally, putting config space into ranges is wrong. It should be in 
'reg'

Rob

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: daire.mcnamara@microchip.com
Cc: aou@eecs.berkeley.edu, bhelgaas@google.com,
	conor.dooley@microchip.com, devicetree@vger.kernel.org,
	krzysztof.kozlowski+dt@linaro.org, kw@linux.com,
	linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
	lpieralisi@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, cyril.jean@microchip.com,
	padmarao.begari@microchip.com, heinrich.schuchardt@canonical.com,
	david.abdurachmanov@gmail.com
Subject: Re: [PATCH v1 4/4] of: PCI: tidy up logging of ranges containing configuration space type
Date: Thu, 8 Sep 2022 15:59:57 -0500	[thread overview]
Message-ID: <20220908205957.GB3240357-robh@kernel.org> (raw)
In-Reply-To: <20220902142202.2437658-5-daire.mcnamara@microchip.com>

On Fri, Sep 02, 2022 at 03:22:02PM +0100, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> PCI ranges can contain addresses where phys.high part can have a type
> of 0, signifying 'configuration space'.  Change
> devm_of_pci_get_host_bridge_resources() to print 'CFG' instead of 'err'
> for a PCI range containing such a 'configuration space' type.

Generally, putting config space into ranges is wrong. It should be in 
'reg'

Rob

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-09-08 21:00 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-02 14:21 [PATCH v1 0/4] PCI: microchip: apportion address translation between rootport and FPGA daire.mcnamara
2022-09-02 14:21 ` daire.mcnamara
2022-09-02 14:21 ` [PATCH v1 1/4] dt-bindings: PCI: microchip: add fabric address translation properties daire.mcnamara
2022-09-02 14:21   ` daire.mcnamara
2022-09-02 16:28   ` Rob Herring
2022-09-02 16:28     ` Rob Herring
2022-09-02 16:51     ` Daire.McNamara
2022-09-02 16:51       ` Daire.McNamara
2022-09-05 14:54     ` Daire.McNamara
2022-09-05 14:54       ` Daire.McNamara
2022-09-08 20:57       ` Rob Herring
2022-09-08 20:57         ` Rob Herring
2022-09-02 14:22 ` [PATCH v1 2/4] riscv: dts: " daire.mcnamara
2022-09-02 14:22   ` daire.mcnamara
2022-09-02 14:29   ` Conor.Dooley
2022-09-02 14:29     ` Conor.Dooley
2022-09-02 14:22 ` [PATCH v1 3/4] PCI: " daire.mcnamara
2022-09-02 14:22   ` daire.mcnamara
2022-09-02 16:49   ` Bjorn Helgaas
2022-09-02 16:49     ` Bjorn Helgaas
2022-09-02 16:54     ` Daire.McNamara
2022-09-02 16:54       ` Daire.McNamara
2022-09-02 14:22 ` [PATCH v1 4/4] of: PCI: tidy up logging of ranges containing configuration space type daire.mcnamara
2022-09-02 14:22   ` daire.mcnamara
2022-09-08 20:59   ` Rob Herring [this message]
2022-09-08 20:59     ` Rob Herring

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