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From: Rob Herring <robh@kernel.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
	James Morse <james.morse@arm.com>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Tony Luck <tony.luck@intel.com>,
	devicetree@vger.kernel.org, Dinh Nguyen <dinguyen@kernel.org>,
	Robert Richter <rric@kernel.org>,
	Punnaiah Choudary Kalluri  <punnaiah.choudary.kalluri@xilinx.com>,
	Manish Narani <manish.narani@xilinx.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-edac@vger.kernel.org, Serge Semin <fancer.lancer@gmail.com>,
	linux-kernel@vger.kernel.org,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	linux-arm-kernel@lists.infradead.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH v2 04/15] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema
Date: Mon, 12 Sep 2022 10:01:55 -0500	[thread overview]
Message-ID: <20220912150155.GA1293565-robh@kernel.org> (raw)
In-Reply-To: <20220910195659.11843-5-Sergey.Semin@baikalelectronics.ru>

On Sat, 10 Sep 2022 22:56:48 +0300, Serge Semin wrote:
> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> are individual IRQs for each ECC and DFI events. The dedicated scrubber
> clock source is absent since it's fully synchronous to the core clock.
> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> registers space.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> ---
> 
> Changelog v2:
> - Keep the alphabetically ordered compatible strings list. (@Krzysztof)
> - Fix grammar nitpicks in the patch log. (@Krzysztof)
> - Drop the PHY CSR region. (@Rob)
> - Move the device bindings to the separate DT-schema.
> ---
>  .../memory-controllers/baikal,bt1-ddrc.yaml   | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
	James Morse <james.morse@arm.com>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Tony Luck <tony.luck@intel.com>,
	devicetree@vger.kernel.org, Dinh Nguyen <dinguyen@kernel.org>,
	Robert Richter <rric@kernel.org>,
	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>,
	Manish Narani <manish.narani@xilinx.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-edac@vger.kernel.org, Serge Semin <fancer.lancer@gmail.com>,
	linux-kernel@vger.kernel.org,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	linux-arm-kernel@lists.infradead.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH v2 04/15] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema
Date: Mon, 12 Sep 2022 10:01:55 -0500	[thread overview]
Message-ID: <20220912150155.GA1293565-robh@kernel.org> (raw)
In-Reply-To: <20220910195659.11843-5-Sergey.Semin@baikalelectronics.ru>

On Sat, 10 Sep 2022 22:56:48 +0300, Serge Semin wrote:
> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> are individual IRQs for each ECC and DFI events. The dedicated scrubber
> clock source is absent since it's fully synchronous to the core clock.
> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> registers space.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> ---
> 
> Changelog v2:
> - Keep the alphabetically ordered compatible strings list. (@Krzysztof)
> - Fix grammar nitpicks in the patch log. (@Krzysztof)
> - Drop the PHY CSR region. (@Rob)
> - Move the device bindings to the separate DT-schema.
> ---
>  .../memory-controllers/baikal,bt1-ddrc.yaml   | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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  parent reply	other threads:[~2022-09-12 15:02 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-10 19:56 [PATCH v2 00/15] EDAC/synopsys: Add generic resources and Baikal-T1 support Serge Semin
2022-09-10 19:56 ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 01/15] dt-bindings: memory: snps: Replace opencoded numbers with macros Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-12 14:18   ` Rob Herring
2022-09-12 14:18     ` Rob Herring
2022-09-21 18:35   ` (subset) " Krzysztof Kozlowski
2022-09-21 18:35     ` Krzysztof Kozlowski
2022-09-10 19:56 ` [PATCH v2 02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-12 14:20   ` Rob Herring
2022-09-12 14:20     ` Rob Herring
2022-09-21 18:35   ` (subset) " Krzysztof Kozlowski
2022-09-21 18:35     ` Krzysztof Kozlowski
2022-09-10 19:56 ` [PATCH v2 03/15] dt-bindings: memory: snps: Convert the schema to being generic Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-12 14:32   ` Rob Herring
2022-09-12 14:32     ` Rob Herring
2022-09-26 10:56     ` Serge Semin
2022-09-26 10:56       ` Serge Semin
2022-09-27 22:02       ` Rob Herring
2022-09-27 22:02         ` Rob Herring
2022-09-28 10:39         ` Serge Semin
2022-09-28 10:39           ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 04/15] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-12  0:44   ` Rob Herring
2022-09-12  0:44     ` Rob Herring
2022-09-12 15:01   ` Rob Herring [this message]
2022-09-12 15:01     ` Rob Herring
2022-09-10 19:56 ` [PATCH v2 05/15] EDAC/synopsys: Add multi-ranked memory support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 06/15] EDAC/synopsys: Add optional ECC Scrub support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 07/15] EDAC/synopsys: Drop ECC poison address from private data Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 08/15] EDAC/synopsys: Add data poisoning disable support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 09/15] EDAC/synopsys: Split up ECC UE/CE IRQs handler Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 10/15] EDAC/synopsys: Add individual named ECC IRQs support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 11/15] EDAC/synopsys: Add DFI alert_n IRQ support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 12/15] EDAC/synopsys: Add reference clocks support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 13/15] EDAC/synopsys: Add ECC Scrubber support Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 14/15] EDAC/synopsys: Drop vendor-specific arch dependency Serge Semin
2022-09-10 19:56   ` Serge Semin
2022-09-10 19:56 ` [PATCH v2 15/15] EDAC/synopsys: Add Baikal-T1 DDRC support Serge Semin
2022-09-10 19:56   ` Serge Semin

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