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From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	jbx6244@gmail.com, cl@rock-chips.com, frank-w@public-files.de,
	s.hauer@pengutronix.de, michael.riesch@wolfvision.net,
	pgwipeout@gmail.com, heiko@sntech.de,
	krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
	vkoul@kernel.org, kishon@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH v4 0/3] rockchip-dsi for rk3568
Date: Mon, 19 Sep 2022 11:46:13 -0500	[thread overview]
Message-ID: <20220919164616.12492-1-macroalpha82@gmail.com> (raw)

From: Chris Morgan <macromorgan@hotmail.com>

This series adds support for the dsi and dphy controllers on the
Rockchip RK3568.

Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance.

Changes since V3:
 - Added labels to bindings in rk356x.dtsi file to make it easier to
   reference in board dts files.

Changes since V2:
 - Removed dsi controller patches, as those have been merged upstream.
 - Removed notes about rolling back clock drivers. If I set the parent
   clock of the VOP port I'm using to VPLL and set the clock rate of
   PLL_VPLL to 500MHz this series works correctly for my panels without
   rolling anything back (per Heiko this is the correct way).
 - Added additional details about refactoring DPHY driver to add
   2.5GHz for rk356x. All other devices still have a max speed of 1GHz.
 - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and
   PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the
   phy_update_bits() works.

Changes since RFCv1:
 - Identified cause of image shift (clock changes).
 - Noted that driver works now.
 - Added devicetree nodes for rk356x.dtsi.

Chris Morgan (3):
  dt-bindings: phy-rockchip-inno-dsidphy: add compatible  for rk3568
  phy/rockchip: inno-dsidphy: Add support for rk3568
  arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to  rk356x

 .../bindings/phy/rockchip,px30-dsi-dphy.yaml  |   1 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  80 +++++++
 .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 204 ++++++++++++++----
 3 files changed, 239 insertions(+), 46 deletions(-)

-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	jbx6244@gmail.com, cl@rock-chips.com, frank-w@public-files.de,
	s.hauer@pengutronix.de, michael.riesch@wolfvision.net,
	pgwipeout@gmail.com, heiko@sntech.de,
	krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
	vkoul@kernel.org, kishon@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH v4 0/3] rockchip-dsi for rk3568
Date: Mon, 19 Sep 2022 11:46:13 -0500	[thread overview]
Message-ID: <20220919164616.12492-1-macroalpha82@gmail.com> (raw)

From: Chris Morgan <macromorgan@hotmail.com>

This series adds support for the dsi and dphy controllers on the
Rockchip RK3568.

Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance.

Changes since V3:
 - Added labels to bindings in rk356x.dtsi file to make it easier to
   reference in board dts files.

Changes since V2:
 - Removed dsi controller patches, as those have been merged upstream.
 - Removed notes about rolling back clock drivers. If I set the parent
   clock of the VOP port I'm using to VPLL and set the clock rate of
   PLL_VPLL to 500MHz this series works correctly for my panels without
   rolling anything back (per Heiko this is the correct way).
 - Added additional details about refactoring DPHY driver to add
   2.5GHz for rk356x. All other devices still have a max speed of 1GHz.
 - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and
   PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the
   phy_update_bits() works.

Changes since RFCv1:
 - Identified cause of image shift (clock changes).
 - Noted that driver works now.
 - Added devicetree nodes for rk356x.dtsi.

Chris Morgan (3):
  dt-bindings: phy-rockchip-inno-dsidphy: add compatible  for rk3568
  phy/rockchip: inno-dsidphy: Add support for rk3568
  arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to  rk356x

 .../bindings/phy/rockchip,px30-dsi-dphy.yaml  |   1 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  80 +++++++
 .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 204 ++++++++++++++----
 3 files changed, 239 insertions(+), 46 deletions(-)

-- 
2.25.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	jbx6244@gmail.com, cl@rock-chips.com, frank-w@public-files.de,
	s.hauer@pengutronix.de, michael.riesch@wolfvision.net,
	pgwipeout@gmail.com, heiko@sntech.de,
	krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
	vkoul@kernel.org, kishon@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH v4 0/3] rockchip-dsi for rk3568
Date: Mon, 19 Sep 2022 11:46:13 -0500	[thread overview]
Message-ID: <20220919164616.12492-1-macroalpha82@gmail.com> (raw)

From: Chris Morgan <macromorgan@hotmail.com>

This series adds support for the dsi and dphy controllers on the
Rockchip RK3568.

Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance.

Changes since V3:
 - Added labels to bindings in rk356x.dtsi file to make it easier to
   reference in board dts files.

Changes since V2:
 - Removed dsi controller patches, as those have been merged upstream.
 - Removed notes about rolling back clock drivers. If I set the parent
   clock of the VOP port I'm using to VPLL and set the clock rate of
   PLL_VPLL to 500MHz this series works correctly for my panels without
   rolling anything back (per Heiko this is the correct way).
 - Added additional details about refactoring DPHY driver to add
   2.5GHz for rk356x. All other devices still have a max speed of 1GHz.
 - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and
   PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the
   phy_update_bits() works.

Changes since RFCv1:
 - Identified cause of image shift (clock changes).
 - Noted that driver works now.
 - Added devicetree nodes for rk356x.dtsi.

Chris Morgan (3):
  dt-bindings: phy-rockchip-inno-dsidphy: add compatible  for rk3568
  phy/rockchip: inno-dsidphy: Add support for rk3568
  arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to  rk356x

 .../bindings/phy/rockchip,px30-dsi-dphy.yaml  |   1 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  80 +++++++
 .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 204 ++++++++++++++----
 3 files changed, 239 insertions(+), 46 deletions(-)

-- 
2.25.1


             reply	other threads:[~2022-09-19 16:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-19 16:46 Chris Morgan [this message]
2022-09-19 16:46 ` [PATCH v4 0/3] rockchip-dsi for rk3568 Chris Morgan
2022-09-19 16:46 ` Chris Morgan
2022-09-19 16:46 ` [PATCH V4 1/3] dt-bindings: phy-rockchip-inno-dsidphy: add compatible " Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-19 16:46 ` [PATCH V4 2/3] phy/rockchip: inno-dsidphy: Add support " Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-19 16:46 ` [PATCH V4 3/3] arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-19 16:46   ` Chris Morgan
2022-09-20  7:03   ` Michael Riesch
2022-09-20  7:03     ` Michael Riesch
2022-09-20  7:03     ` Michael Riesch
2022-09-20  6:10 ` [PATCH v4 0/3] rockchip-dsi for rk3568 Vinod Koul
2022-09-20  6:10   ` Vinod Koul
2022-09-20  6:10   ` Vinod Koul
2022-09-23 10:34 ` (subset) " Heiko Stuebner
2022-09-23 10:34   ` Heiko Stuebner
2022-09-23 10:34   ` Heiko Stuebner
2022-09-23 15:19   ` Philip C

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