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From: Li Yang <leoyang.li@nxp.com>
To: shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Li Yang <leoyang.li@nxp.com>,
	Laurentiu Tudor <laurentiu.tudor@nxp.com>
Subject: [PATCH v3 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
Date: Thu, 22 Sep 2022 16:40:26 -0500	[thread overview]
Message-ID: <20220922214030.9004-6-leoyang.li@nxp.com> (raw)
In-Reply-To: <20220922214030.9004-1-leoyang.li@nxp.com>

LS1046a is mostly dma coherent with a few exceptions(e.g. edma) so add
the dma-coherent property at the soc level in the device tree and drop
the instances where it's specifically added to a few select devices.
Also use the newly added dma-noncoherent property for exceptions.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 27033c558e3e..2a445c455b6b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
 		#size-cells = <2>;
 		ranges;
 		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+		dma-coherent;
 
 		ddr: memory-controller@1080000 {
 			compatible = "fsl,qoriq-memory-controller";
@@ -355,7 +356,6 @@ crypto: crypto@1700000 {
 			ranges = <0x0 0x00 0x1700000 0x100000>;
 			reg = <0x00 0x1700000 0x0 0x100000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			dma-coherent;
 
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.4-job-ring",
@@ -708,6 +708,7 @@ edma0: dma-controller@2c00000 {
 					    QORIQ_CLK_PLL_DIV(2)>,
 				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(2)>;
+			dma-noncoherent;
 		};
 
 		usb0: usb@2f00000 {
@@ -794,7 +795,6 @@ pcie1: pcie@3400000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -834,7 +834,6 @@ pcie2: pcie@3500000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -874,7 +873,6 @@ pcie3: pcie@3600000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
-- 
2.37.1


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WARNING: multiple messages have this Message-ID (diff)
From: Li Yang <leoyang.li@nxp.com>
To: shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Li Yang <leoyang.li@nxp.com>,
	Laurentiu Tudor <laurentiu.tudor@nxp.com>
Subject: [PATCH v3 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
Date: Thu, 22 Sep 2022 16:40:26 -0500	[thread overview]
Message-ID: <20220922214030.9004-6-leoyang.li@nxp.com> (raw)
In-Reply-To: <20220922214030.9004-1-leoyang.li@nxp.com>

LS1046a is mostly dma coherent with a few exceptions(e.g. edma) so add
the dma-coherent property at the soc level in the device tree and drop
the instances where it's specifically added to a few select devices.
Also use the newly added dma-noncoherent property for exceptions.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 27033c558e3e..2a445c455b6b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
 		#size-cells = <2>;
 		ranges;
 		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+		dma-coherent;
 
 		ddr: memory-controller@1080000 {
 			compatible = "fsl,qoriq-memory-controller";
@@ -355,7 +356,6 @@ crypto: crypto@1700000 {
 			ranges = <0x0 0x00 0x1700000 0x100000>;
 			reg = <0x00 0x1700000 0x0 0x100000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			dma-coherent;
 
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.4-job-ring",
@@ -708,6 +708,7 @@ edma0: dma-controller@2c00000 {
 					    QORIQ_CLK_PLL_DIV(2)>,
 				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(2)>;
+			dma-noncoherent;
 		};
 
 		usb0: usb@2f00000 {
@@ -794,7 +795,6 @@ pcie1: pcie@3400000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -834,7 +834,6 @@ pcie2: pcie@3500000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -874,7 +873,6 @@ pcie3: pcie@3600000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			dma-coherent;
 			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
-- 
2.37.1


  parent reply	other threads:[~2022-09-22 21:43 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22 21:40 [PATCH v3 0/9] accumulated dts updates for ls1046a Li Yang
2022-09-22 21:40 ` Li Yang
2022-09-22 21:40 ` [PATCH v3 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 2/9] arm64: dts: ls1046a: Add the PME interrupt and big-endian to PCIe EP nodes Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` Li Yang [this message]
2022-09-22 21:40   ` [PATCH v3 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang
2022-09-22 21:40 ` [PATCH v3 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGA Li Yang
2022-09-22 21:40   ` Li Yang
2022-09-22 21:40 ` [PATCH v3 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang
2022-09-22 21:40   ` Li Yang
2022-10-23 13:24 ` [PATCH v3 0/9] accumulated dts updates for ls1046a Shawn Guo
2022-10-23 13:24   ` Shawn Guo

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