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From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: palmer@dabbelt.com, damien.lemoal@opensource.wdc.com,
	geert@linux-mk68.org, heiko@sntech.de, kernel@esmil.dk,
	arnd@arndb.de, Conor Dooley <conor.dooley@microchip.com>
Subject: [RFC 18/27] riscv: convert SOC_VIRT to ARCH_VIRT
Date: Fri, 23 Sep 2022 19:55:57 +0100	[thread overview]
Message-ID: <20220923185605.1900083-19-conor@kernel.org> (raw)
In-Reply-To: <20220923185605.1900083-1-conor@kernel.org>

From: Conor Dooley <conor.dooley@microchip.com>

As per discussion at LPC, the SOC_ prefaced symbols are to be converted
to an ARCH_ prefix for consistency between "incumbent" vendors and
those with a legacy in other architectures. Rename SOC_VIRT to ARCH_VIRT.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig.socs                 | 2 +-
 arch/riscv/configs/defconfig            | 2 +-
 arch/riscv/configs/nommu_virt_defconfig | 2 +-
 arch/riscv/configs/rv32_defconfig       | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 811338720cbd..9a216deb5c9c 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -21,7 +21,7 @@ config ARCH_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 
-config SOC_VIRT
+config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select CLINT_TIMER if RISCV_M_MODE
 	select POWER_RESET
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index bfb6f6f57ae2..341202b90c7f 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -28,7 +28,7 @@ CONFIG_PROFILING=y
 CONFIG_ARCH_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_STARFIVE=y
-CONFIG_SOC_VIRT=y
+CONFIG_ARCH_VIRT=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y
diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig
index 1a56eda5ce46..9ad6a182d932 100644
--- a/arch/riscv/configs/nommu_virt_defconfig
+++ b/arch/riscv/configs/nommu_virt_defconfig
@@ -24,7 +24,7 @@ CONFIG_EXPERT=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLOB=y
 # CONFIG_MMU is not set
-CONFIG_SOC_VIRT=y
+CONFIG_ARCH_VIRT=y
 CONFIG_NONPORTABLE=y
 CONFIG_SMP=y
 CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
index 4badab395546..ffa5e8f05ae6 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -17,7 +17,7 @@ CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
 CONFIG_PROFILING=y
 CONFIG_ARCH_SIFIVE=y
-CONFIG_SOC_VIRT=y
+CONFIG_ARCH_VIRT=y
 CONFIG_NONPORTABLE=y
 CONFIG_ARCH_RV32I=y
 CONFIG_SMP=y
-- 
2.37.3


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  parent reply	other threads:[~2022-09-23 18:58 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23 18:55 [RFC 00/27] RISC-V: Convert SOC_FOO symbols to ARCH_FOO Conor Dooley
2022-09-23 18:55 ` [RFC 01/27] clk: microchip: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP Conor Dooley
2022-09-28 12:16   ` Christoph Hellwig
2022-09-28 12:51     ` Conor Dooley
2022-09-23 18:55 ` [RFC 02/27] i2c: microchip-corei2c: " Conor Dooley
2022-09-23 18:55 ` [RFC 03/27] mailbox: mpfs: " Conor Dooley
2022-09-23 18:55 ` [RFC 04/27] usb: musb: " Conor Dooley
2022-09-23 18:55 ` [RFC 05/27] rtc: " Conor Dooley
2022-09-23 18:55 ` [RFC 06/27] riscv: stop selecting the PolarFire SoC clock driver Conor Dooley
2022-09-23 18:55 ` [RFC 07/27] riscv: replace SOC_STARFIVE with ARCH_STARFIVE Conor Dooley
2022-09-23 19:09   ` Heiko Stuebner
2022-09-23 19:14     ` Conor Dooley
2022-09-23 19:20       ` Heiko Stuebner
2022-09-23 19:22         ` Conor Dooley
2022-09-23 18:55 ` [RFC 08/27] clk: starfive: " Conor Dooley
2022-09-23 18:55 ` [RFC 09/27] pinctrl: " Conor Dooley
2022-09-23 18:55 ` [RFC 10/27] reset: " Conor Dooley
2022-09-23 18:55 ` [RFC 11/27] riscv: replace SOC_SIFIVE with ARCH_SIFIVE Conor Dooley
2022-09-23 18:55 ` [RFC 12/27] soc: sifive: convert SOC_SIFIVE to ARCH_SIFIVE Conor Dooley
2022-09-23 18:55 ` [RFC 13/27] clk: " Conor Dooley
2022-09-23 18:55 ` [RFC 14/27] clk: sifive: select by default if ARCH_SIFIVE Conor Dooley
2022-09-23 18:55 ` [RFC 15/27] serial: " Conor Dooley
2022-09-23 18:55 ` [RFC 16/27] PCI: dwc: fu740: convert SOC_SIFIVE to ARCH_SIFIVE Conor Dooley
2022-09-23 18:55 ` [RFC 17/27] riscv: stop selecting SiFive clock and serial drivers directly Conor Dooley
2022-09-23 18:55 ` Conor Dooley [this message]
2022-09-23 18:55 ` [RFC 19/27] kunit: tool: rename SOC_VIRT to ARCH_VIRT in riscv's QEMU config Conor Dooley
2022-09-23 18:55 ` [RFC 20/27] wireguard: selftests: swap SOC_VIRT for ARCH_VIRT on riscv Conor Dooley
2022-09-24 10:03   ` Jason A. Donenfeld
2022-09-23 18:56 ` [RFC 21/27] riscv: convert SOC_CANAAN to ARCH_CANAAN Conor Dooley
2022-09-23 18:56 ` [RFC 22/27] clk: k210: " Conor Dooley
2022-09-23 18:56 ` [RFC 23/27] pinctrl: " Conor Dooley
2022-09-23 18:56 ` [RFC 24/27] soc: " Conor Dooley
2022-09-23 18:56 ` [RFC 25/27] reset: " Conor Dooley
2022-09-23 18:56 ` [RFC 26/27] serial: sifive: select by default if ARCH_CANAAN Conor Dooley
2022-09-23 18:56 ` [RFC 27/27] riscv: stop directly selecting drivers for ARCH_CANAAN Conor Dooley
2022-09-23 18:59 ` [RFC 00/27] RISC-V: Convert SOC_FOO symbols to ARCH_FOO Conor Dooley
2022-09-26  1:50 ` Damien Le Moal
2022-09-26  8:02   ` Conor Dooley
2022-09-26  9:04 ` Geert Uytterhoeven
2022-09-27  6:34   ` Conor Dooley
2022-09-27  6:48     ` Arnd Bergmann
2022-09-27  6:57       ` Conor Dooley
2022-09-27  7:03         ` Geert Uytterhoeven

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