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From: Stephen Boyd <sboyd@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: Re: [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks
Date: Fri, 07 Oct 2022 13:47:06 -0700	[thread overview]
Message-ID: <20221007204707.EB279C433D6@smtp.kernel.org> (raw)
In-Reply-To: <cover.1665147497.git.geert+renesas@glider.be>

Quoting Geert Uytterhoeven (2022-10-07 06:09:59)
>         Hi Mike, Stephen,
> 
> This patch series adds the various SASYNCPER clocks (used by modules
> that must not be affected by Spread Spectrum and/or Fractional
> Multiplication), and most of its derived module clocks (serial and PWM)
> on the R-Car V4H (R8A7799G0) SoC.
> 
> As the second patch is a fix, and the first patch is a dependency (also
> for a related DT fix), I plan to queue the first two patches in
> renesas-clk-fixes for v6.1.
> I plan to queue the last three patches in renesas-clk for v6.2.
> 
> Thanks for your comments!
> 
> Geert Uytterhoeven (5):
>   clk: renesas: r8a779g0: Add SASYNCPER clocks
>   clk: renesas: r8a779g0: Fix HSCIF parent clocks
>   clk: renesas: r8a779g0: Add SCIF clocks
>   clk: renesas: r8a779g0: Add PWM clock
>   clk: renesas: r8a779g0: Add TPU clock
> 

Thanks for the heads up

Acked-by: Stephen Boyd <sboyd@kernel.org>

      parent reply	other threads:[~2022-10-07 20:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-09 21:20   ` Wolfram Sang
2022-10-10 11:15     ` Geert Uytterhoeven
2022-10-10 18:34       ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
2022-10-10  7:46   ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-10  7:46   ` Wolfram Sang
2022-10-07 20:47 ` Stephen Boyd [this message]

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