From: Wolfram Sang <wsa@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock
Date: Mon, 10 Oct 2022 09:46:27 +0200 [thread overview]
Message-ID: <Y0PN06dSfFi6NAUW@shikoro> (raw)
In-Reply-To: <f2c1e2c5411b7bd6af726e6baf6e1efc354a7cdf.1665147497.git.geert+renesas@glider.be>
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On Fri, Oct 07, 2022 at 03:10:04PM +0200, Geert Uytterhoeven wrote:
> Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
> Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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next prev parent reply other threads:[~2022-10-10 7:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-09 21:20 ` Wolfram Sang
2022-10-10 11:15 ` Geert Uytterhoeven
2022-10-10 18:34 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang [this message]
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
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