Re: [RFC PATCH 5/6] hw/cxl/cxl-events: Add event interrupt support

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Mon, 10 Oct 2022 15:29:43 -0700
ira.weiny@intel.com wrote:

> From: Ira Weiny <ira.weiny@intel.com>
> 
> To facilitate testing of event interrupt support add a QMP HMP command
> to reset the event logs and issue interrupts when the guest has enabled
> those interrupts.
Two things in here, so probably wants breaking into two patches:
1) Add the injection command
2) Add the interrupt support.

As on earlier patches, I think we need a more sophisticated
injection interface so we can inject individual errors (or better yet sets of
errors so we can trigger single error case, and multiple error per interrupt.)

Jonathan


> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> ---
>  hmp-commands.hx             | 14 +++++++
>  hw/cxl/cxl-events.c         | 82 +++++++++++++++++++++++++++++++++++++
>  hw/cxl/cxl-host-stubs.c     |  5 +++
>  hw/mem/cxl_type3.c          |  7 +++-
>  include/hw/cxl/cxl_device.h |  3 ++
>  include/sysemu/sysemu.h     |  3 ++
>  6 files changed, 113 insertions(+), 1 deletion(-)
> 
> diff --git a/hmp-commands.hx b/hmp-commands.hx
> index 564f1de364df..c59a98097317 100644
> --- a/hmp-commands.hx
> +++ b/hmp-commands.hx
> @@ -1266,6 +1266,20 @@ SRST
>    Inject PCIe AER error
>  ERST
>  
> +    {
> +        .name       = "cxl_event_inject",
> +        .args_type  = "id:s",
> +        .params     = "id <error_status>",
> +        .help       = "inject cxl events and interrupt\n\t\t\t"
> +                      "<id> = qdev device id\n\t\t\t",
> +        .cmd        = hmp_cxl_event_inject,
> +    },
> +
> +SRST
> +``cxl_event_inject``
> +  Inject CXL Events
> +ERST
> +
>      {
>          .name       = "netdev_add",
>          .args_type  = "netdev:O",


>  const MemoryRegionOps cfmws_ops;
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 2b13179d116d..b4a90136d190 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -459,7 +459,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
>      ComponentRegisters *regs = &cxl_cstate->crb;
>      MemoryRegion *mr = &regs->component_registers;
>      uint8_t *pci_conf = pci_dev->config;
> -    unsigned short msix_num = 3;
> +    unsigned short msix_num = 7;
>      int i;
>  
>      if (!cxl_setup_memory(ct3d, errp)) {
> @@ -502,6 +502,11 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
>          msix_vector_use(pci_dev, i);
>      }
>  
> +    ct3d->cxl_dstate.event_vector[CXL_EVENT_TYPE_INFO] = 6;
> +    ct3d->cxl_dstate.event_vector[CXL_EVENT_TYPE_WARN] = 5;
> +    ct3d->cxl_dstate.event_vector[CXL_EVENT_TYPE_FAIL] = 4;
> +    ct3d->cxl_dstate.event_vector[CXL_EVENT_TYPE_FATAL] = 3;

For testing purposes, maybe put 2 of them on same interrupt vector?
That way we'll verify the kernel code deals fine with either separate
interrupts or shared vectors.