From: Dinh Nguyen <dinguyen@kernel.org>
To: jh80.chung@samsung.com
Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: [PATCHv5 0/6] arm: socfpga: use clk-phase-sd-hs
Date: Wed, 19 Oct 2022 12:06:51 -0500 [thread overview]
Message-ID: <20221019170657.68014-1-dinguyen@kernel.org> (raw)
Hi,
Just wanted to address the comments regarding the dt-bindings
document of "altr,sysmgr-syscon". I ran the 'make dt_binding_check'
after: pip3 install dtschema --upgrade and I checked to make sure I have
yamllint installed and I still don't see any warnings. I'm also confused
about whether "altr,socfpga-dw-mshc" should be a const. I see the same
usage in:
Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
allOf:
- $ref: "mmc-controller.yaml#"
- if:
properties:
compatible:
contains:
const: arasan,sdhci-5.1
Please advise on how to address this comment!
Thanks,
Dinh
Dinh Nguyen (6):
dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase
clk: socfpga: remove the setting of clk-phase for sdmmc_clk
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
.../bindings/mmc/synopsys-dw-mshc.yaml | 32 ++++++++-
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
.../boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 +
.../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
arch/arm/boot/dts/socfpga_arria5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 +
.../boot/dts/altera/socfpga_stratix10.dtsi | 1 +
.../dts/altera/socfpga_stratix10_socdk.dts | 1 +
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 +
.../boot/dts/intel/socfpga_agilex_socdk.dts | 1 +
.../boot/dts/intel/socfpga_n5x_socdk.dts | 1 +
drivers/clk/socfpga/clk-gate-a10.c | 68 -------------------
drivers/clk/socfpga/clk-gate.c | 60 ----------------
drivers/clk/socfpga/clk.h | 1 -
drivers/mmc/host/dw_mmc-pltfm.c | 43 +++++++++++-
17 files changed, 83 insertions(+), 135 deletions(-)
--
2.25.1
next reply other threads:[~2022-10-19 17:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 17:06 Dinh Nguyen [this message]
2022-10-19 17:06 ` [PATCHv5 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen
2022-10-19 23:31 ` Rob Herring
2022-10-20 23:01 ` Rob Herring
2022-10-20 18:20 ` Krzysztof Kozlowski
2022-10-19 17:06 ` [PATCHv5 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 3/6] arm: " Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen
2022-10-21 13:32 ` Krzysztof Kozlowski
2022-10-21 15:17 ` Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Dinh Nguyen
2022-10-19 17:06 ` [PATCHv5 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Dinh Nguyen
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